Samsung Electronics Co., Ltd.

Dong Ku Kang

Jun Jin Kong

Sung Chung Park

Dong Hyuk Chae

Seung Jae Lee

Seung-Hwan Song

Young Hwan Lee

Kyoung Lae Cho

Nam Phil Jo

Chan Kim

Seung-Bum Kim

Sung-Jae Byun

Young Hee Lee

Bong Soon Lim

Kyung Hwa Yun

Si Hoon Hong

Se Won Yun

Kyung Min Kang

Jae Woong Hyun

Tae-young Kim

Yun Tae Lee

Dae Seok Byeon

Young Ho Lim

Kyong Lae Cho

Sun-Jun Park

Chan Ho Kim

Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Page buffer and memory device including the same

A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.

Semiconductor memory device including capacitor

A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a first substrate, a horizontal semiconductor layer disposed on a second substrate, a plurality of stack structures on the horizontal semiconductor layer in a first direction, wherein the plurality of stack structures include a memory cell region and a capacitor region, a plurality of electrode isolation regions extending in the first direction and a second direction and configured to separate the plurality of stack structures to be connected to the horizontal semiconductor layer and a plurality of through-via structures having a first side connected to a through channel contact through at least one metal pad, wherein a capacitor is formed between each of electrode pads and at least one of electrode isolation regions in the plurality of stack structures or at least one of the plurality of through-via structures.

A nonvolatile memory device is programmed by decoding a received address, determining whether the received address is a first type of page address or a second type of page address, adjusting a maximum verify time of a program loop used to verify a program state of page data according to the determined type of page address, and performing a verify operation during the adjusted maximum verify time.

Method and apparatus for adjusting maximum verify time in nonvolatile memory device

A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string select line. The method includes programming a first sub-block of the memory block, determining in the non-volatile memory device when a reference word line is programmed during programming of the first sub-block, and partial erasing a second sub-block of the memory block upon determining that the reference word line is programmed during programming of the first sub-block.

Non-volatile memory devices and systems including the same, and methods of programming non-volatile memory devices

A multi-level cell (MLC) memory device may include 'a' number of m-bit MLC memory cells; an encoder that encodes 'k' bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, &#x2018;a&#x2019; and &#x2018;m&#x2019; may be integers greater than or equal to 2, &#x2018;k&#x2019; and &#x2018;n&#x2019; may be integers greater than or equal to 1, and &#x2018;n&#x2019; may be greater than &#x2018;k&#x2019;. A method of storing data in the device may include encoding &#x2018;k&#x2019; bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding &#x2018;n&#x2019; bits of data at a code rate of n/k to generate a decoded bit stream.

Multi-level cell memory devices and methods of storing data in and reading data from the memory devices

A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

Multi-level cell memory device and method thereof

An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

Error control code apparatuses and methods of using the same

An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.

A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Multi-level cell memory devices using trellis coded modulation and methods of storing data in and reading data from the memory devices

A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.

Method and apparatus for controlling reading level of memory cell

The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.

Apparatus for reading data and method using the same

Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.

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Seongnam-si, South Korea

Dong Ku Kang