Samsung Electronics Co., Ltd.

Dong-Ku Kang

Seung-Jae Lee

Young-Ho Lim

Jun-Jin Kong

Dong-Hyuk Chae

Seung-Bum Kim

Hee-Won Lee

Seung-Hwan Song

Sang-gu Kang

Sang-Yong Yoon

Boh-Chang Kim

Joon-Suc Jang

Jae-Duk Yu

Sang-In Park

Chul-Bum Kim

Bu-il Nam

Hyeong-Jun Kim

Sung-Chung Park

Dae-Yeal Lee

In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.

Data storage apparatus, coding unit, systems including the same, method of coding and method of reading data

A memory device may include an input/output control unit for receiving input signals through an input/output bus, and a control logic unit for receiving control signals, and when the control signals satisfy first through fourth conditions, the control logic unit identifies a command, an address, data and an identifier of the memory device in the input signals, and latches the input signals. The fourth condition is different from the first through third conditions.

Memory device and a memory system including the same

A non-volatile memory device and a method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical direction over a substrate and connected to n word lines, wherein n is an integer greater than or equal to 3. The method includes programming memory cells of second to n&#x2212;1-th word lines, from among first to n-th word lines that are sequentially disposed in the vertical direction over the substrate, to a multi-level state, wherein a multi-level program operation is sequentially performed from the second to n&#x2212;1-th word lines in an order in which the word lines are disposed; and programming memory cells of the first word line to a single level state after the programming memory cells of the second to n&#x2212;1-th word lines to a multi-level state.

Non-volatile memory device and method of programming the same

A method of operating a nonvolatile memory device includes performing a first memory operation on a first memory block of a plurality of memory blocks and a curing operation on a portion of the first memory block when a status signal indicates a ready state of the nonvolatile memory device during an interval equal to or greater than a reference interval after the first memory operation is completed. The nonvolatile memory device includes the plurality of memory blocks, each memory block including a plurality of vertical strings extending in a vertical direction with respect to a substrate.

Methods of operating nonvolatile memory devices, and memory systems including nonvolatile memory devices

A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data. A control logic unit includes a verification operation controller configured to selectively perform, based on a result of comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.

Programmed data verification for a semiconductor memory device

A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N&#x3e;2), wherein, in the consecutive verify read operations, the bitlines are placed in a precharged state by precharging them to a first level during a verification period of memory cells programmed in the first logic state, are maintained in the precharged state during verification periods of memory cells programmed in the second to (N&#x2212;1)-th logic states, and are discharged after a verification period of memory cells programmed in the N-th logic state.

Nonvolatile memory device maintaining a bitline precharge during program verification periods for multi-level memory cells and related programming method

A method of testing a non-volatile memory device and a method of managing the non-volatile memory device are provided. The method of testing the non-volatile memory device includes calculating first and second values based on program loop frequencies corresponding to word lines of a memory area. A characteristic value of the memory area may be calculated based on the first and second values, and may be compared to a reference value to determine whether the memory area is defective.

Method of testing non-volatile memory device and method of managing non-volatile memory device

A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

Over-sampling read operation for a flash memory device

A flash memory device includes a memory cell array, a temperature sensing unit, and a control unit. The memory cell array is configured to store a plurality of pieces of configuration data corresponding to respective temperature levels of the flash memory device, the pieces of configuration data indicative of respective operation parameter values of the flash memory device. The temperature sensing unit is configured to measure an ambient temperature of the flash memory device and to generate temperature level data. The a control unit is configured to receive the temperature level data from the temperature sensing unit, to read a piece of configuration data corresponding to the temperature level data from among the plurality of pieces of configuration data stored in the memory cell array, and to set operation parameters of the flash memory device according to an operation parameter value indicated by the read piece of configuration data.

Flash memory device and memory system including the same

A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Npage programming operations, where N is an integer of 2 or more. The programming sequence further includes an erase programming that is executed after the (N&#x2212;1)page programming operation and before the Npage programming operation, where the erase page programming increases a threshold voltage distribution of erase cells among the MLC memory cells.

Nonvolatile memory device and system, and method of programming a nonvolatile memory device

A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.

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Yongin-si, South Korea

Dong-Ku Kang