Applied Materials, Inc.

Patterson + Sheridan Llp

Dong-Kil Yim

Soo Young Choi

Tae Kyung Won

John M White

Beom Soo Park

Quanyuan Shang

Suhail Anwar

Seon-Mee Cho

Yi Cui

Chung-Hee Park

Yan Ye

Jozef Kudela

Xuena Zhang

Shinichi Kurita

Woong-Kwon Kim

Makoto Inagawa

Jrjyan Jerry Chen

William Reid Harshbarger

Lai Zhao

Takako Takehara

Hans Georg Wolf

Rodney Shunleong Lim

Ikuo Mori

Duk-Chul Yun

Han Byoul Kim

Mark Hsiao

Jin Man Ha

Youn-Gyung Chang

Remegio Manacio

Dennis Zvalo

Steven Verhaverbeke

Robert Jan Visser

Kam S Law

Robin L Tiner

Xiangxin Rui

Kurtis Leschkies

Yujia Zhai

Sam Hyungsam Kim

Harvey You

Wan-Yu Lin

Jung Bae Kim

Robert I Greene

Jriyan Jerry Chen

Young Jin Choi

Wenqing Dai

Yun-chu Tsai

Won Ho Sung

Hsiao-Lin Yang

Hao-Chien Hsu

Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Plasma treatment on metal-oxide TFT

In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO) and hafnium dioxide (HfO). The coating material includes a compound selected from alumina (AlO), yttrium-containing compounds, and combinations thereof.

Selective in-situ cleaning of high-k films from processing chamber using reactive gas precursor

Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

Thin film transistor with small storage capacitor with metal oxide switch

Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Interface engineering for high capacitance capacitor for liquid crystal display

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

Surface treatment process performed on devices for TFT applications

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between a metal electrode layer and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a metal electrode layer disposed on a barrier layer formed above a gate insulating material layer, an interface layer disposed on the metal electrode layer, wherein the interface layer is an oxygen free dielectric material layer sized to be formed predominately on the metal electrode layer, and an insulating material layer disposed on the interface layer, wherein the insulating material layer is an oxygen containing dielectric layer.

Thin film transistor fabrication utlizing an interface layer on a metal electrode layer

Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide layer and treating the metal oxide layer with a fluorine containing gas or plasma. The fluorine treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

Oxygen vacancy of IGZO passivation by fluorine treatment

The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

Multilayer passivation or etch stop TFT

The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple substrates are disposed on opposite sides of the processing source within the processing chamber, yet the processing environments are not isolated from each other. The processing source is a horizontally centered vertical plasma generator that permits multiple substrates to be processed simultaneously on either side of the plasma generator, yet independent of each other. The system is arranged as a twin system whereby two identical processing lines, each with their own processing chamber, are arranged adjacent to each other. Multiple robots are used to load and unload the substrates from the processing system. Each robot can access both processing lines within the system.

Vertical inline CVD system

The present invention generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises IGZO or zinc oxide. After the source and drain electrodes are formed, but before the passivation layers or etch stop layers are deposited thereover, the active channel is exposed to an NO or Oplasma. The interface between the active channel and the passivation layers or etch stop layers are either altered or damaged during formation of the source and drain electrodes. The NO or Oplasma alters and repairs the interface between the active channel and the passivation or etch stop layers.

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Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid crystal display (LCD) and organic light-emitting diode (OLED) displays.

SiON gradient concept

Growing community of inventors

Pleasanton, CA, United States of America

Dong-Kil Yim