Samsung Electronics Co., Ltd.

Dong-Jun Seong

Soon-Oh Park

Hideki Horii

Dong-Ho Ahn

Youn-Seon Kang

Seol Young Choi

Jin-Woo Lee

Jeong-Hee Park

Jung-dal Choi

Gyu-Hwan Oh

Seung-Jae Jung

Zhe Wu

Sung-Ho Eun

Seong-Geon Park

Jung-Moo Lee

Yong-Jin Park

Min-kyu Yang

Jun-Hwan Paik

A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

Memory device and method of manufacturing the same

A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.

Semiconductor devices

A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.

Variable resistance memory device

A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below,[GeSi(AsTe)][N]&#x2003;&#x2003;(1)

Memory device

A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.

Variable resistance memory device and method of manufacturing the same

A semiconductor diode includes a first semiconductor pattern including a first impurity, a first diffusion barrier pattern on the first semiconductor pattern, an intrinsic semiconductor pattern on the first diffusion barrier pattern, a second diffusion barrier pattern on the intrinsic semiconductor pattern, and a second semiconductor pattern including a second impurity on the second diffusion barrier pattern.

Semiconductor diodes, and variable resistance memory devices

A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.

Growing community of inventors

Seongnam-si, South Korea

Dong-Jun Seong