Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Dong-Ju Yang

Shin-Il Choi

Yu-Gwang Jeong

Ki-Yeup Lee

Seung-Ha Choi

Sang-Gab Kim

Je-Hun Lee

Do-Hyun Kim

Jae-Hyoung Youn

Hong-Kee Chin

Pil-Sang Yun

Ki-Won Kim

Woo-Geun Lee

Young-Wook Lee

Kap-Soo Yoon

Byeong-Beom Kim

Hye-Young Ryu

Jean-Ho Song

Sun-Young Hong

Young-Joo Choi

Yun-Jong Yeo

Kyoung-Jae Chung

Jong-Hyun Choung

Bong-Kyun Kim

Ji-Young Park

Yang-Ho Bae

Jae-Hong Kim

Chang-Oh Jeong

Min-Seok Oh

Jong-in Kim

Shi-Yul Kim

Joo-han Kim

Eun-Guk Lee

Sung-Ryul Kim

Hee-Joon Kim

Hwa-Yeul Oh

Hyangyul Kim

Seung-Jae Jung

Chang-Hoon Kim

Yeo-Geon Yoon

Jung-Suk Bang

O-Sung Seo

Je-Hyeong Park

Ki-Yong Song

Nam-Seok Suh

Tae-Hyung Ihn

Pil-Soon Hong

Sung-Hen Cho

Dong-Hoon Lee

Wang Woo Lee

O Sung Seo

Jean Ho Song

Hwa Yeul Oh

Beomsoo Park

Tae-Woo Kim

Hyungchul Kim

Yu Gwang Jeong

Yang Ho Bae

Eunhye Park

Jiyun Hong

Chang-Ho Jeong

Sun-young Hong

Seungjin Kim

Jeongeum Lee

Junki Lee

Nam Seok Suh

A display substrate includes a base substrate with a display area and a light-blocking area around the display area, a switching element disposed on the base substrate that includes a gate electrode electrically connected to a gate line extending in a first direction, a source electrode electrically connected to a data line extending in a second direction crossing the first direction, and a drain electrode spaced apart from the source electrode, a color filter layer disposed on the switching element, a first electrode disposed on the color filter layer, an insulation layer disposed on the first electrode, a second electrode disposed on the insulation layer that includes a slit, a dummy pattern disposed on substantially the same layer as the second electrode that overlaps the data line, and a data light-blocking pattern directly disposed on the dummy pattern that has substantially the same width as the data line.

Display substrate and method of manufacturing the same

A display panel includes a first base substrate, a gate line disposed on the first base substrate and extending in a first direction, a gate electrode electrically connected to the gate line, a thin film transistor including an active pattern which includes a source area, a drain area and a channel area overlapping the gate electrode, a common electrode disposed on the first base substrate, where a common voltage is applied to the common electrode, an auxiliary common electrode line electrically connected to the common electrode, and including an opaque metal, a pixel electrode electrically connected to the thin film transistor, and disposed on the common electrode to overlap the common electrode, and a cover electrode connected to the auxiliary common electrode line, and overlapping the channel area.

Display panel and method of manufacturing the same

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Thin film transistor panel having an etch stopper on semiconductor

A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Thin film transistor substrate and the method thereof

A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

Contact portion of wire and manufacturing method thereof

A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

Method of fabricating a thin film transistor array substrate

A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

Method for manufacturing thin film transistor array panel

A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SFor SF/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.

A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.

Thin film transistor array panel and method for manufacturing the same

Growing community of inventors

Seoul, South Korea

Dong-Ju Yang