Samsung Electronics Co., Ltd.

Dong-hyun Sohn

Hye-Jin Kim

Chul-woo Park

Sang-beom Kang

Ho-Young Song

Kyo-Min Sohn

Yun-sang Lee

Sang-Joon Hwang

Cheol Su Kim

Dong-seok Kang

Chan-Kyung Kim

Jong-hyun Ryu

Hyung-Rok Oh

Yong-ho Kim

Hong-suk Kim

Jin Ra

Moon-il Jung

Soo-Ho Cha

Joo-ho Kim

Hyung-rock Oh

Hyun-min Song

Kyu-Chan Lee

Chul-Sung Park

Sang-Bo Lee

Dong-min Kim

Sang-Kyu Kang

Chi-sung Oh

Jae-hoon Cha

Hyeong-jin Jang

A range hood and a method for controlling the range hood are provided. The apparatus includes a range hood which is capable of photographing a cooking process that is being performed on an upper plate of a cook top by using a camera disposed in the main body of the range hood, and a method for controlling the range hood are provided. In some of the example embodiments, a range hood is capable of photographing a cooking process that is being performed on an upper plate of a cook top that is positioned below a bottom surface of the main body.

Range hood and method for controlling the range hood

An electronic apparatus, including an emissive display configured to provide a first image having a first image quality; a transparent display disposed on the emissive display and configured to provide a second image having a second image quality; and a controller configured to control the emissive display to provide the first image in according to first mode and control the transparent display to provide the second image according to a second mode.

Electronic apparatus including emissive display and transparent display and method of controlling same

A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Spin transfer torque magnetic random access memory for supporting operational modes with mode register

Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Device and method for repairing memory cell and memory system including the device

A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Semiconducotr memory device including non-volatile memory cell array

A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

Semiconductor memory devices for alternately selecting bit lines

A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

Semiconductor memory device having resistive memory cells and method of testing the same

A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.

Magneto-resistive memory device including source line voltage generator

Growing community of inventors

Hwaseong-si, South Korea

Dong-hyun Sohn