Samsung Electronics Co., Ltd.

Dong-Hyun Han

Joo-Sung Park

Seok-Han Park

Seong-Ki Ryu

Han-Sub Jung

Sun-Ho Moon

The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.

Method of fabricating semiconductor device including process monitoring pattern having overlapping input/output pad array area

Semiconductor device including process monitoring pattern having overlapping input/output pad array area

A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other.

Semiconductor wafer including guard ring patterns and process monitoring patterns

A semiconductor device including a plurality of decoupling capacitors formed on a semiconductor substrate, and a plurality of decoupling capacitor contact plugs disposed between the semiconductor substrate and the plurality of decoupling capacitors, the plurality of decoupling capacitor contact plugs being electrically connected to the plurality of decoupling capacitors and including an array of first decoupling capacitor contact plugs and second decoupling capacitor contact plugs.

Semiconductor decoupling capacitor device

A semiconductor device includes a process monitoring pattern overlapping with an input/output (I/O) pad. The semiconductor device may include a semiconductor substrate having a cell array region and a peripheral circuit array region, and a plurality of process monitoring patterns disposed in the peripheral circuit array region. The semiconductor device may further include a plurality of input/output (I/O) pads, where each I/O pad is disposed on a corresponding process monitoring pattern.

Semiconductor device, semiconductor module, and electronic apparatus including process monitoring pattern overlapping with I/O pad

A photomask includes a first region, a second region and a third region. The first and second regions are spaced apart by the third region. A first photomask type is disposed in the first region and a second photomask type, different from the first photomask type, is disposed in the second region. A dummy photomask pattern is disposed in the third region and is structured to form a dummy wafer pattern on a wafer.

Hybrid photomask and method of fabricating the same

An alignment key structure in a semiconductor device is provided. The alignment key structure includes an insulation layer formed on a substrate, and a passivation layer pattern formed on the insulation layer. The insulation layer includes a plurality of metal wirings. The passivation layer pattern includes a first opening that exposes at least one of the metal wirings. Moreover, the first opening has a width which is narrower than a width of the exposed metal wiring.

Growing community of inventors

Gunpo-si, South Korea

Dong-Hyun Han