Samsung Electro-mechanics Co., Ltd.

Korea Advanced Institute of Science and Technology

Korea Electronics Technology Institute

Chung Ang University Industry Academic Cooperation

Dong Hyun Baek

Yu Sin Kim

Sun Woo Yun

Sung Hwan Park

Youn Suk Kim

Sun Woo Yoon

Youngjin Kim

Sang Hoon Park

Sang Hee Kim

Ki Jin Kim

Kwang Ho Ahn

Jeong-Yun Lee

Young Jin Kim

Sun-Woo Yun

Seoung Yeoung Son

Eun Su Kim

Jin Young Lee

A DC-DC converter device and a sub DC-DC converter unit with parallel structure included in the same are disclosed. The DC-DC converter device includes a main DC-DC converter unit configured to receive a (-)th reference voltage, a (-)th reference voltage and a (n&#x2212;1)th output voltage, and output an nth first output current corresponding to an nth output voltage; and a sub DC-DC converter unit configured to receive a second reference voltage and the (n&#x2212;1)th output voltage, and output an nth second output current corresponding to the nth output voltage. Here, an output current in accordance with the nth output voltage corresponds to sum of the nth first output current and the nth second output current.

DC-DC converter device and sub DC-DC converter of parallel structure included therein

Disclosed herein is a power generating circuit including a first transistor in which a second control signal is applied to a control terminal and a first control signal is applied to one end, and which has the other end connected to an output terminal, a second transistor in which the first control signal is applied to a control terminal and the second control signal is applied to one end, and which has the other end connected to the output terminal a third transistor in which one of the first and the second control signals is applied to a control terminal and which has one end grounded, and a fourth transistor in which the other one thereof is applied to a control terminal and which has one end connected to the other end of the third transistor and the other end connected to the output terminal.

Power generating circuit and switching circuit

The power generating circuit includes: a first transistor having a control terminal to which a second control signal is applied and one end to which a first control signal is applied; and a second transistor having a control terminal to which the first control signal is applied and one end to which the second control signal is applied, wherein the other ends of the first transistor and the second transistor are connected to an output terminal.

An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.

Inverter and switching circuit

A down-frequency conversion circuit and up-frequency conversion circuit, and a receiver and transmitter applying the same are provided. The down-frequency conversion circuit includes a harmonic mixer and general mixer, and thus becomes able to convert frequency using one LO (Local Oscillator) frequency, thereby reducing burden on generating LO frequency.

Down-converter, up-converter, receiver and transmitter applying the same

An RF switch circuit includes an RF switch including a first NMOS switch formed on a chip substrate, a switch controller including a second NMOS switch and a PMOS switch formed on the substrate, for controlling the RF switch, and a limiter including a deep N-type well diode formed on the substrate, for limiting an RF signal level transferred from the RF switch to the switch controller through the substrate. The first NMOS switch includes a first N-type terminal formed on a deep N-type well substrate formed on the substrate, for receiving a driving power through a first floating resistor, a P-type terminal for receiving a body power through a second floating resistor, and two second N-type terminals for receiving a gate power through a third floating resistor. The P-type and two second N-type terminals are formed on a P-type substrate formed on the deep N-type well substrate.

Radio frequency switch circuit

A radio frequency (RF) switch circuit in which an RF switch and a switch controller are formed on a single CMOS substrate and floating resistors are connected to a deep N type well substrate, an N type well substrate, and a P type well substrate to thereby increase linearity with respect to input power. In the RF switch having at least one NMOS (N type Metal Oxide Semiconductor) switch changing a transmission path of an RF signal, an N type terminal formed on a first deep N type well substrate receives driving power through a floating resistor, a P type terminal formed on a first P type substrate receives body power through a floating resistor, and the two N type terminals formed on the first P type substrate receive gate power through a floating resistor, and in the switch controller having at least one NMOS switch and at least one PMOS (P type Metal Oxide Semiconductor) switch controlling changing of a path of the RF switch, an N type terminal formed on a second deep N type well substrate and an N type terminal formed on the first N type substrate receive driving power through floating resistors.

Growing community of inventors

Seoul, South Korea

Dong Hyun Baek