Advanced Micro Devices Corporation

Spansion LLC.

Cypress Semiconductor Corporation

Dong-Hyuk Ju

William George En

Srinath Krishnan

Imran Khan

Emi Ishida

Bin Yu

Shibly S Ahmed

Chuan Lin

Jun Kang

Richard M Fastow

Scott Luning

Concetta E Riccobene

Hsiao-Han Thio

David W Wu

Xilin Judy An

Qi Xiang

Zoran Krivokapic

Scott Allan Bell

Effiong Etukudo Ibok

Judy Xilin An

Olov B Karlsson

Robert B Ogle

Akif Sultan

Mario M Pelella

Richard K Klein

Don Draper

Sheung Hee Park

Daniel A Steckert

Ahmed Shibly

Nga-Ching (Alan) Wong

Siu Lun Lee

A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

Controlling the latchup effect

A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.

Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Junction leakage suppression in memory devices

Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.

Method to obtain multiple gate thicknesses using in-situ gate etch mask approach

The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.

Dual SOI film thickness for body resistance control

A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of the buried insulation layer, the oxide trap region having a plurality of oxide traps to promote carrier recombination.

SOI device with structure for enhancing carrier recombination and method of fabricating same

The present invention is a method for fabricating a memory device. In one embodiment, an impurity concentration is created in a semiconductor substrate of a memory device. An annealing process is then performed. A second impurity concentration is created in a second region of the semiconductor substrate and a second annealing process is performed.

Method for fabricating a memory device

The present invention is a high voltage transistor formation method and system that includes a varying or gradient concentration lightly doped drain and source implant region. The lightly doped drain (LDD) implant region has gradient concentration characteristics that provide a higher concentration under a source and drain and lower concentration close to a surface source drain channel formation under a gate. A lightly doped drain tilt implant process is utilized to form a component area (e.g., a transistor source and/or drain area) with gradient doping profiles. The varying concentration profile provides a smooth electrical characteristic transformation between regions that reduces the probability of hot electron generation otherwise associated with electrical fields that cross abrupt changes between different conductivity orientation regions. The higher concentration of the light dopants at the bottom of the source and drain regions also helps reduce the probability of deep junction breakdown.

High voltage transistor scaling tilt ion implant method

A flash memory cell of the present invention comprises a floating gate, having a charge trapping region and a fin region. A source region and a drain region is formed proximate the floating gate. A control gate is formed above the charge trapping region of the floating gate. The fin region advantageously reduces leakage current, thereby allowing further scaling of the cell.

Flash memory cell having reduced leakage current

A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure

An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

SOI MOSFET having amorphized source drain and method of fabrication

A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

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Cupertino, CA, United States of America

Dong-Hyuk Ju