Samsung Electronics Co., Ltd.

Dong Hyeon Jang

Sa Yoon Kang

Nam Seog Kim

Yong Hwan Kwon

Heung Kyu Kwon

Gu S Kim

Ho Jin Lee

In Young Lee

Seung Duk Baek

Kang Wook Lee

Min Kyo Cho

Ha Young Yim

Jae Sik Chung

A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.

Microelectronic devices including multiple through-silicon via structures on a conductive pad and methods of fabricating the same

An electronic module comprises a monolithic microelectronic substrate including at least one integrated circuit die, e.g., a plurality of unseparated memory dice or a mixture of different types of integrated circuit dice. The monolithic substrate further includes a redistribution structure disposed on the at least one integrated circuit die and providing a connector contact coupled to the at least one integrated circuit die. For example, the connector contact may be configured as edge connector contact for the module. The redistribution structure may be configured to provide a passive electronic device, e.g., an inductor, capacitor and/or resistor, electrically coupled to the at least one integrated circuit die and/or the redistribution structure may comprise at least one conductive layer configured to provide electrical connection to a contact pad of an electronic device mounted on the substrate. Methods of fabricating electronic modules are also discussed.

Wafer-level electronic modules with integral connector contacts

In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP is mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Chip scale packages manufactured at wafer level

A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.

Wafer level stack chip package and method for manufacturing same

A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.

Semiconductor package

method for manufacturing a semiconductor package

In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

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Seoul, South Korea

Dong Hyeon Jang