Samsung Electronics Co., Ltd.

Dong Hun Kwak

Chi Weon Yoon

Sang Wan Nam

Jong-chul Park

Seul Bee Lee

Yo Han Lee

Han Jun Lee

Wan Dong Kim

A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.

Nonvolatile memory device and method for operating with varying programming time

A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

Memory device

Nonvolatile memory device with verification signal to indicate success or failure of programming memory cell and method for operating thereof

A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.

Memory device with voltage controller

A memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including the plurality of memory cells, and a driving determination unit determining whether to perform at least one of a pre-charging operation, a development operation and a latching operation of page buffers connected to the memory cells provided with the read voltage.

A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.

Growing community of inventors

Hwaseong-si, South Korea

Dong Hun Kwak