Taiwan Semiconductor Manufacturing Comp. Ltd.

Dong-Hsu Cheng

Peng-Ren Chen

Jia-Guei Jou

Yung-Hsiang Chen

Chi-Ta Lu

Chih-Chung Huang

Ming-Ho Tsai

Wei-Yu Su

Li-Kong Turn

Jyun-Hong Chen

Kuang-Hung Lin

Deng-Guey Juang

Ru-Gun Liu

Tsai-Sheng Gau

Wen-Chun Huang

Chih-Chiang Tu

Chun-Jen Chen

Ming-Hui Chih

Chia-Ping Chiang

Chang-Cheng Hung

Cheng-Ku Chen

Yung-Haw Liaw

Chang-Jyh Hsieh

Yi-Hsu Chen

Jian-Huei Lee

Kuan-Chi Chen

Yi-Hsien Chen

Yung Haw Liaw

Cheng-Wei Huang

Jim Liang

Jun-Hua Chen

Yung-Pei Chin

Hsiao Chih Chang

Li-Kong Tern

Jeen-Hao Liu

The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron&#xd7;10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Structure and method for E-beam in-chip overlay mark

The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.

Structure and method for E-beam writing

A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.

System and method for lithography exposure with correction of overlay shift induced by mask heating

A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Layout decomposition method

The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Lithography performance check methods and apparatus

A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Mask making with error recognition

The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Cycle time reduction in data preparation

Provided is a photomask that includes a substrate having a first region and a second region, a first pattern disposed in the first region of the substrate, and a second pattern disposed in the second region of the substrate. The first and second patterns are a decomposition of a design pattern to be transferred onto a wafer in a lithography process.

Superimpose photomask and method of patterning

A static resistant reticle comprises a substrate and a patterning layer and is covered by an antistatic conductive film of quaternary amine (RN)Cl. A pellicle structure comprising an optically transparent membrane tightly stretched on a frame is also coated by an antistatic electro conductive film of a similar material. The reticle with the pellicle form a shielded structure isolating the reticle from ESD.

Reticle with antistatic coating

A pod for transporting reticles is made with a reticle support that has a &#x3a0;-shape and is provided with pins, whose arrangement matches the location of chrome-free areas on a reticle base. Due to that, the pins, when supporting the reticle, come into contact with the reticle in chrome-free areas thereof. Thus, scratching the metallic areas and releasing metallic particles is prevented from occurring.

Reticle pod and reticle with cut areas

A mask pattern having an anti-ESD ring which protects the pattern region of the mask from damage due to ESD events. The anti-ESD ring has a space between two broad border regions formed of an opaque metal such as chrome. ESD fingers, or rods extend from one of the border regions to within a small gap of the other border region. These ESD fingers act as lightning rods so that ESD events preferably occur across this small gap between the ESD fingers and one of the border regions. The ESD fingers are small enough so that any metal transferred across the gap in an ESD event is very small. The gap is located so that any metal transferred is far away from the pattern region of the mask. The ESD fingers confine ESD events to a preferred region of the mask and damage to the pattern region is avoided.

Electrostatic discharge damage prevention method on masks

An electrostatic discharge-free container equipped with a metal shield for holding an insulating article therein is described. In the container, an electrically conductive layer substantially covers a bottom lid made of a non-conductive material so as to sufficiently shield the insulating article from electrostatic discharge damages. The present invention novel ESD-free container may further be provided with a metal knob situated in a top lid of the container, or be provided with a metal enclosure positioned inside the container between the top lid and the insulating article. The metal layer that substantially overlaps the bottom lid may be injection molded as an insert in the bottom lid, or may be coated or plated on the bottom lid. The present invention novel ESD-free container eliminates any electrostatic discharge from occurring on a reticle plate and thus avoiding any potential damages. The present invention ESD-free reticle pod may be easily modified from existing reticle pod and therefore provides a low cost retrofit method for providing ESD-free containers.

Electrostatic discharge-free container equipped with metal shield

The present invention discloses a method and apparatus for controlling air flow in a liquid coating apparatus by providing an adjustable housing that consists of an upper compartment and a lower compartment such that the height of the cavity contained therein can be adjusted. Subsequently, the spacing between a substrate to be coated and the interior wall of the upper compartment can be suitably adjusted to allow a desirable quantity of air flowing therethrough. The redeposition of liquid coating particles thrown off the substrate surface during a spin coating process and then bouncing back from the interior wall of the upper compartment onto the substrate surface can be prevented. The contamination of the substrate surface can therefore be eliminated or reduced. The present invention adjusting means may further include a removable roof member which can be turned by thread means to adjust the spacing between the bottom surface of the roof member and the substrate resulting in an adjustable air flow rate through such spacing.

Growing community of inventors

Tainan, Taiwan

Dong-Hsu Cheng