Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Dong-hoon Baek

Young-min Choi

Jae-Youl Lee

Eun-young Jin

Jaeyoul Lee

Hyun-Wook Lim

Jae-youl Lee

Kyong-ho Kim

Dong-Myung Lee

Han-su Pae

Kwi-sung Yoo

Ji-Hoon Kim

Hyunwook Lim

Kwi Sung Yoo

Jae-Yoon Sim

Kwi-Sung Yoo

Kyongho Kim

Youngmin Choi

Jung-Pil Lim

Young-Hun Lee

Kil-Hoon Lee

Jung-pil Lim

Han-Su Pae

A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.

Method of operating source driver, display driving circuit, and method of operating display driving circuit

A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.

Operating method of receiver, source driver and display driving circuit including the same

A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

Clock and data recovery circuit detecting unlock of output of phase locked loop

The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.

Display driving circuit

A timing controller, a source driver, and a display driver integrated circuit (DDI) having improved test efficiency and a method of operating the DDI are provided. The timing controller includes a code generation unit for generating a first code from display data, a protocol encoder for generating a data sequence including the display data and the first code, and a transmission unit for providing the data sequence to a source driver through a link.

Timing controller, source driver, and display driver integrated circuit having improved test efficiency and method of operating display driving circuit

A display driver circuit, including a source driver configured to drive source lines of a display panel, and a timing controller configured to transfer image data to the source driver and to control the source driver such that the transferred image data is displayed via the display panel, the timing controller also being configured to transfer to the source driver a control signal and a test pattern, which are used to test a bit error rate, and the source driver being configured to test the bit error rate of the transferred test pattern in response to the transferred control signal.

Display driver circuit, operating method thereof, and user device including the same

According to an example embodiment, a display driving integrated circuit (IC) includes a timing controller and a plurality of source drivers. The timing controller is configured to output a plurality of signals to the plurality of source drivers, and at least one of the timing controller and the plurality of source drivers operates in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period. According to an example embodiment, a mode conversion method used in a display driving IC includes switching between a normal mode to a power down mode in response to a standby control signal. The power down mode is implemented on at least one of a timing controller and a plurality of source drivers included in the display driving IC in at least one of an initializing period, a data transmission period, and a vertical blank period.

Mode conversion method, and display driving integrated circuit and image processing system using the method

A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Clock and data recovery circuit of a source driver and a display device

Display driver circuits include a multi-function driver, which is configured to support first and second modes of operation. The multi-function driver supports the first mode of operation in response to a first control signal by driving a bus with an output signal, which has a value that indicates a locked or unlocked status of a clock signal therein. The multi-function driver also supports the second mode of operation in response to a second control signal by driving the bus with multi-bit data that is unrelated to the locked or unlocked status of the clock signal.

Display driver circuits having multi-function shared back channel and methods of operating same

A system for transmitting and receiving a signal includes a transmitter that switches a first reference voltage and a second reference voltage and generates first and second voltage signals, and a receiver the receives the first and second voltage signals. The transmitter includes a reference voltage generator that generates the first reference voltage and the second reference voltage, and a switch block that switches the first reference voltage and the second reference voltage and outputs the first and second voltage signals. The receiver includes a resistor having two terminals to which the first and second voltage signals are applied.

Growing community of inventors

Seoul, South Korea

Dong-hoon Baek