Samsung Electronics Co., Ltd.

Dong-Ho Park

Seung-Keun Lee

Jong-Min Park

Myong-Jae Kim

A flash memory device is disclosed that includes a control circuit for generating a count-up pulse signal notifying a generation of an address required for a burst read operation. An address generator circuit generates an address in response to the count-up pulse signal, and a discharge circuit discharges global bit lines in response to the count-up pulse signal. According to this control scheme, the global bit lines may be discharged before the local and global bit lines are selected.

Flash memory device capable of reducing read time

We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.

Multi level flash memory device and program method

A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Method of repairing a failed wordline

Provided is a programming method of a flash memory device. The method includes programming a memory cell for a first programming time, detecting whether or not the memory cell is programmed and terminating a first programming period when it is detected that the memory cell is programmed, determining whether or not the first programming period is terminated when it is detected that the memory cell is not programmed, repeating programming for a first programming time, detecting, and determining until the first programming period is terminated, programming the memory cell for a second programming time, detecting whether or not the memory cell is programmed and terminating a second programming period when it is detected that the memory cell is programmed, determining whether or not the second programming period is terminated when it is detected that the memory cell is not programmed, and repeating programming for a second programming time, detecting, and determining until the second programming time is terminated.

Programming method of flash memory device

Non-volatile semiconductor memory device

A non-volatile memory device of the present invention comprises a memory cell array having a plurality of cells, a plurality of dummy bit lines, a plurality of dummy word lines. At least one of the dummy bit lines includes a bulk tapping for applying bulk voltage. Here, P.sup.+ impurity is implanted into the dummy bit lines. With this improved memory structure, a device layout area can be reduced and an increase in bulk voltage resulting from hot carriers can be suppressed.

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Gyeonggi-do, South Korea

Dong-Ho Park