Samsung Electronics Co., Ltd.

Dong-Ho Hyun

Young-Uk Chang

Seok-Won Hwang

Jin-Sung Kim

Gil-Shin Moon

An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator. The drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode.

Semiconductor memory device and on-die termination circuit

A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.

Semiconductor device, test system and method of testing on die termination circuit

A memory device includes a plurality of test mode signal generating units and a plurality of test circuits. Each test mode signal generating unit generates a respective test mode signal for a respective test circuit. The test mode signal generating units generate the test mode signals in series for the test circuits. Each test mode signal generating unit may be disposed within a respective test circuit such that wiring is not necessary from the source of the test mode signals to the test circuits.

Generation of test mode signals in memory device with minimized wiring

An integrated circuit memory device may include a memory cell array, a plurality of data input/output pins, and a plurality of input/output circuits coupled to respective data input/output pins. The input/output circuits may be configured to accept respective data bits being written to the memory cell array from the respective data input/output pins during a write operation, and the input/output circuits may be configured to provide respective data bits being read from the memory cell array to the respective data input/output pins during a read operation. In addition, the input/output circuits may be configured to modify operational characteristics thereof responsive to respective control bits received through the respective data input/output pins during a mode set operation. Related methods and systems are also discussed.

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Gyeonggi-do, South Korea

Dong-Ho Hyun