Samsung Electronics Co., Ltd.

Hyundai Mobis Co., Ltd.

Dong-Ho Ahn

Hideki Horii

Zhe Wu

Jeong-Hee Park

Soon-Oh Park

Seong-Geon Park

Jung-Moo Lee

Seol Young Choi

Jin-Woo Lee

Young-Lim Park

Yong-Ho Ha

Geum-Jong Bae

Hyeong-Geun An

Joon-Sang Park

Young-kuk Kim

Sung-Lae Cho

Jun-Young Jang

Dong-Jun Seong

Han-Bong Ko

Dong-Won Lim

Young-Soo Lim

Ho-Kyu Kang

Gyeo-Re Lee

Chul-Sung Kim

Jun-Soo Bae

Byoung-Deog Choi

Tai-Su Park

Jung-il Lee

Do-hyung Kim

Ja-Hum Ku

Jong-Uk Kim

Jae-Yoon Yoo

Sug-hun Hong

Soo-Jin Hong

Jung-hwan Park

Man-Sug Kang

Kyung-won Park

Moon-Han Park

Ho-kyu Kang

Chul-Joon Choi

Jin-ho Oh

Min-kyu Yang

Mi-lim Park

Dong-jun Seong

Su-Hwan Ji

Jun-Ku Ahn

A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Variable resistance memory device and method of manufacturing the same

A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

Memory device

A memory device is provided. The memory device includes a variable resistance layer. A selection device layer is electrically connected to the variable resistance layer. The selection device layer includes a chalcogenide switching material having a composition according to chemical formula 1 below,[GeSeTe][X]&#x2003;&#x2003;(1)

Memory device including a variable resistance material layer

A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.

Variable resistance memory devices

A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below,[GeSi(AsTe)][N]&#x2003;&#x2003;(1)

A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.

A variable resistance material layer including germanium (Ge), antimony (Sb), tellurium (Te), and at least one type of impurities X. The variable resistance material layer having a composition represented by a chemical formula of X(GeSbTe), wherein an atomic concentration of the impurities X is in a range of 0&#x3c;p&#x2266;0.2, an atomic concentration of Ge is in a range of 0.05&#x2266;a&#x3c;0.19, and an atomic concentration of Te is in a range of 0.42&#x2266;b&#x2266;0.56.

Variable resistance material layers and variable resistance memory devices including the same

In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.

Method of manufacturing a phase change memory device

Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups.

Methods of manufacturing non-volatile phase-change memory devices

A nonvolatile memory cell includes a substrate and a phase changeable pattern configured to retain a state of the memory cell, on the substrate. An electrically insulating layer is provided, which contains a first electrode therein in contact with the phase changeable pattern. The first electrode has at least one of an L-shape when viewed in cross section and an arcuate shape when viewed from a plan perspective. A lower portion of the first electrode may be ring-shaped when viewed from the plan perspective. The lower portion of the first electrode may also have a U-shaped cross-section. An upper portion of the first electrode may also have an arcuate shape that spans more than 180&#xb0; of a circular arc.

Nonvolatile memory cells having phase changeable patterns therein for data storage

Phase change memory devices may be fabricated by forming a first electrode on a substrate and forming a chalcogenide material on the first electrode. The chalcogenide material is plasma treated sufficiently to induce a plasma species throughout the chalcogenide material. A second electrode is formed on the chalcogenide material. Related devices are also described.

Plasma treating methods of fabricating phase change memory devices, and memory devices so fabricated

Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.

Methods of forming phase change memory devices having bottom electrodes

A memory device includes first and second electrodes and a phase-changeable material region disposed between the first and second electrodes and including first and second portions contacting respective ones of the first and second electrodes and a third portion interconnecting the first and second portions and configured to preferentially heat with respect to the first and second portions responsive to a current passing between the first and second electrodes. The first and second portions of the phase-changeable material region may contact respective ones of the first and second electrodes at respective first and second electrode contact surfaces and the third portion may have a cross-sectional area that is less than areas of each of the first and second contact surfaces. For example, the third portion may include a filament portion extending between the first and second portions.

Memory device including phase-changeable material region and method of fabricating the same

A phase change memory device may include an integrated circuit substrate and first and second phase change memory elements on the integrated circuit substrate. The first phase change memory element may include a first phase change material having a first crystallization temperature. The second phase change memory element may include a second phase change material having a second crystallization temperature. Moreover, the first and second crystallization temperatures may be different so that the first and second phase change memory elements are programmable at different temperatures. Related methods and systems are also discussed.

Phase change memory devices including memory cells having different phase change materials and related methods and systems

Growing community of inventors

Hwaseong-si, South Korea

Dong-Ho Ahn