Skhynix Inc.

Dong Ham Yim

Young Guen Choi

Young Hoon Cha

Dae Hoon Jang

Dong Wook Kim

Joon Ho Lee

Cheon Ok Jeong

Jeong Sun Park

A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.

Memory system, memory controller and operating method thereof

The present technology relates to an electronic device. A storage device includes a memory device including pages, a buffer memory configured to store address mapping information including a mapping relationship between logical addresses provided from a host and physical addresses corresponding to the pages, first trim bitmap information including trim information of first logical address groups each including a first number of logical addresses having at least two of the logical addresses, and second trim bitmap information including trim information of second logical address groups each including a second number of logical addresses greater than the first number of the logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.

Storage device and method of operating the same for processing a trim request of host

Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method. The present disclosure may divide user data and map data corresponding to the user data into data segments, may input the data segments in N virtual die queues, and may program the same in a memory device, wherein a user data segment input in the virtual die queue is programmed according to two program schemes, thereby quickly programming the user data and the map data in the memory device and quickly updating the map data in a map cache.

Memory system, memory controller, and operation method

A memory system includes a memory controller. The memory controller includes: a buffer memory configured to store read count values of memory blocks and address mapping information of the memory blocks; and a central processing unit configured to monitor the read count values, and determine whether a refresh operation of target blocks, among the memory blocks, is to be performed on all memory blocks including target blocks in a super block, in a unit of the super block or on the target memory blocks in the super block in a unit of a single block, based on the monitoring result.

Growing community of inventors

Gyeonggi-do, South Korea

Dong Ham Yim