Samsung Electronics Co., Ltd.

Dong-Hak Shin

Seung-Hoon Lee

Seong-Jin Jang

Dong-Wook Kim

Jong-hyun Choi

Kyu-Chan Lee

Young-Hun Kim

Ho-Sung Song

Byung-sik Moon

In-Chul Jeong

Young-Yong Byun

Jin-seok Kwak

Jong-Min Oh

Soo-Hwan Kim

Ki-Won Park

Sung-Min Yim

Hyun-chul Yoon

Hyuk-joon Kwon

Yong-Sang Park

Sung-Jun Her

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows; and a data control circuit configured to, sequentially read a first unit of data from N memory cell rows of the plurality of memory cell rows, generate merged test results by comparing bits read from the first units of the N memory cell rows, and output the merged test results, during the test mode of the semiconductor memory device. Therefore, test time for testing the semiconductor memory device may be greatly reduced because a test device may determine pass/fail of the data of the unit of repair unit on one read operation.

Semiconductor memory devices and memory systems including the same

A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

Sense amplifier circuit and semiconductor memory device

A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Semiconductor memory devices having bit lines

A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.

Semiconductor memory device including signal controller connected between memory blocks

A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminals and an input terminal to select a buffer. The input-output buffers are coupled to the data input-output terminals respectively. The memory core is coupled to the input-output buffers through input-output lines. The buffer selecting unit generates a parallel buffer select signal based on an expected signal having a pulse stream, wherein the expected signal is provided via the input terminal to select a buffer in a test mode, and applies the parallel buffer select signal to the plurality of input-output buffers to select a corresponding input-output buffer. Hence, the semiconductor memory device may increase efficiency of a pin in a test device.

Semiconductor memory device having a single input terminal to select a buffer and method of testing the same

A driver circuit for an integrated circuit device includes a transistor that has a gate terminal, a source terminal, and a bulk substrate terminal. The source terminal is connected to the bulk substrate terminal. A pull-up circuit is connected between a power supply node and the source terminal. The pull up circuit is configured to increase a voltage at the source terminal and the bulk substrate terminal of the transistor responsive to a control signal.

Driver circuits for integrated circuit devices that are operable to reduce gate induced drain leakage (GIDL) current in a transistor and methods of operating the same

A semiconductor memory device includes a row decoder, a control circuit, and a memory cell array having an open bit-line structure. The memory cell array includes a plurality of word lines coupled to the row decoder, a plurality of bit lines, a plurality of memory cells, a plurality of sense amplifier blocks, and a plurality of burn-in voltage supply lines coupled to the plurality of sense amplifier blocks in a predetermined order, respectively. The control circuit controls the row decoder and the memory cell array for performing a burn-in test. During the burn-in test, the burn-in voltage supply lines are provided with at least two different burn-in voltages. The burn-in voltage supply lines respectively coupled to the sense amplifier blocks that are adjacent to each other are provided with different burn-in voltages during the burn-in test.

Semiconductor memory device capable of writing different data in cells coupled to one word line during burn-in test

A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection line voltage generator to generate a column selection line voltage; and a column selection line driver to provide the column selection line signal based at least in at the column selection line voltage level.

Semiconductor memory device

A semiconductor memory device includes a memory cell array, and first and second boosting voltage generating portions. The first boosting voltage generating portion generates a first driving signal when the semiconductor device operates in an active mode and supplies a boosting voltage that is higher than a power supply voltage to an output terminal in response to the first driving signal. The second boosting voltage generating portion includes a first boosting voltage generator generating a second driving signal when a level of the boosting voltage of the output terminal is below a target level in the active mode and pumping the boosting voltage in response to the second driving signal and a second boosting voltage generator pumping the boosting voltage in response to the first driving signal when first memory cell array blocks are selected and pumping the boosting voltage in response to the second driving signal when second memory cell array blocks are selected.

Plural bank semiconductor memory device with increased boosting voltage stability

A data access circuit of a semiconductor memory device in which data is read and written via all multiple ports in the semiconductor memory device having a multi-port structure. The data access circuit device having a multi-port structure comprises a write controller, a plurality of ports to receive serial data to be written, a plurality of read/write data control units, a plurality of write buffer units, a read controller, an input/output sense amplifier, and a plurality of read buffer units. Test time for the semiconductor memory device can be shortened by doubling the number of ports even in low frequency equipment, thus improving the throughput, by allowing data to be simultaneously and divisionally accessed via all ports, instead of accessing the data via a specified port at a time.

Data access circuit of semiconductor memory device

A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminals and an input terminal to select a buffer. The input-output buffers are coupled to the data input-output terminals respectively. The memory core is coupled to the input-output buffers through input-output lines. The buffer selecting unit generates a parallel buffer select signal based on an expected signal having a pulse stream, wherein the expected signal is provided via the input terminal to select a buffer in a test mode, and applies the parallel buffer select signal to the plurality of input-output buffers to select a corresponding input-output buffer. Hence, The semiconductor memory device may increase efficiency of a pin in a test device.

A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

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Hwaseong-si, South Korea

Dong-Hak Shin