Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Dong-gyu Kim

Sang-Soo Kim

Byoung-Sun Na

Jun-ho Song

Woon-yong Park

Won-hee Lee

In-sik Jang

Yong-gug Bae

Jong-in Choung

Jung-Hee Lee

Joo-Hyung Lee

Mee-Hye Jung

Woon-Yong Park

Jun-Ho Song

Kyung-seop Kim

Kyung-nam Lee

Shi-yual Kim

Tae-Sung Kim

Seung-Jun Lee

Jong-Woong Chang

Seung-Soo Baek

Bong-Hyun You

Hye-Seok Na

Dong-Hyeon Ki

Se-Hyoung Cho

Jae-Ho Huh

Joo-hyung Lee

Gyu-Su Lee

Sang-Chul Lee

Min-Sung Choi

Jin-Kwan Kim

Il-Koo Nah

Joong-hee Lee

You-sik Chun

Yong-guk Pae

Seong-bae Cho

Jeong-Weon Seo

Wan-Bae Kim

A liquid crystal display (LCD) panel includes a substrate, a plurality of parallel control lines on the substrate, and a bonding pad area on the substrate having a plurality of bonding pads therein. A respective one of a plurality of interconnecting conductors connect a respective bonding pad of the bonding pad area to a respective one of the plurality of parallel control lines, each of the plurality of interconnecting conductors having a uniform resistance. According to embodiments of the invention, an interconnecting conductor of the plurality of interconnecting conductors may include a material selected to provide the uniform resistance. The interconnecting conductor may include a first portion including a first material having a first resistivity and a second portion including a second material having a second resistivity different from the first resistivity. The first and second portions may have respective first and second lengths selected to provide the uniform resistance. According to other embodiments, an interconnecting conductor of the plurality of interconnecting conductors may have a width selected to provide the uniform resistance. In one embodiment, the plurality of interconnecting conductors have a resistivity per unit length associated therewith and extend from the bonding pad area in a fanned configuration, with the resistivity of the interconnecting conductors increasing toward a medial portion of the fanned configuration. The width of the interconnecting conductors may decrease towards the medial portion of the fanned configuration to produce the desired resistivity. According to other embodiments, an interconnecting conductor of the plurality of interconnecting conductors has a length selected to provide the uniform resistance. In one embodiment, the interconnecting conductor has a serpentine portion to provide the desired length.

Liquid crystal display panels having control lines with uniform resistance

The amorphous silicon layer overlaps the gate electrode and the edges of the amorphous silicon layer are substantially encompassed by the edges of the gate electrode. The distance between the edges is at least 2 microns. Accordingly, both the light obliquely incident on the amorphous silicon layer from the outside once the light normally incident on the amorphous silicon layer is blocked by the gate electrode. Insulation layers, which are separated from the amorphous silicon layer and made of an amorphous silicon, are interposed between the edges of the source/drain electrodes and the gate electrode to reinforce the insulation between the gate electrode and the source/drain electrodes and also to absorb the light reflected by the source/drain electrodes and the gate electrode. The source electrode may partially surround the drain electrode in annular shape, to reduce the parasitic capacitance generated between the gate electrode and the drain electrode. The amorphous silicon layer may protrude out the gate electrode near the edges of the gate electrode which encompasses a source electrode and the source/drain electrodes. The amorphous silicon layer covers the edges of the gate electrode which encompasses the source electrode. The source electrode may be curved to prolong the distance between the drain electrode and the portion of the amorphous silicon layer.

Thin film transistors for liquid crystal displays

A matrix-type display device having a repair layout, particularly, a matrix-type display device which can be repaired in a pixel unit, is provided. Two or more of signal lines such as scanning signal lines, displaying signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the displaying signal lines and scanning signal lines, the short of the pixel electrode and signal line, and the loss of electrode of a switching element, can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Matrix-type display device capable of being repaired in pixel unit

Active matrix display devices having improved opening and contrast ratios utilize light blocking lines to improve display contrast ratios yet position the light blocking lines on the same level of metallization as the gate lines to thereby limit parasitic capacitive coupling between the data lines and the pixel electrodes. The light blocking lines are also positioned on only one side of the data lines so that improvements in the display's opening ratio can also be achieved. The light blocking lines are preferably patterned so that no overlap occurs between a display's data lines and the light blocking lines. The elimination of overlap reduces the step height in the display's pixel electrodes and thereby reduces the extent of disclination of the liquid crystal molecules in the liquid crystal material extending opposite the pixel electrodes. The light blocking lines are also preferably patterned beneath the display's data lines so that parasitic capacitive coupling between the data lines and the pixel electrodes is reduced. The light blocking lines are also preferably formed with beveled edges so that the step height in the display's pixel electrodes can be reduced even further.

Active matrix display devices having improved opening and contrast ratios and methods of forming same and a storage electrode line

Disclosed is a simplified method for manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad, and a gate electrode is formed on the substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, the first portion of the photoresist pattern that is located between the source electrode and the drain electrode is thinner than the second portion that is located on the data wire, and the rest of the photoresist layer are wholly removed. The thin portion is made by controlling the exposure or by a reflow process to form a thin portion. And exposure is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer. Next, the exposed portions of conductor layer are removed by wet etch or dry etch, thereby the ohmic contact layer thereunder is exposed. Then the exposed ohmic contact layer and the semiconductor layer thereunder are removed by dry etching along with the first portion of the photoresist layer. The residue of the photoresist layer is removed by ashing. Source/drain electrodes are separated by removing the portion of the conductor layer at the channel and the ohmic contact layer pattern thereunder. Then, the second portion of the photoresist layer is removed, and a passivation layer, a pixel electrode, a redundant gate pad, and a redundant data pad are formed.

Thin film transistor array panel and a method for manufacturing the same

The present invention applies different common voltages to common electrodes corresponding to both end points of gate lines and data lines. At this time, the highest common voltage is applied to a common electrode point far away from both a data driver and a gate driver, the second highest common voltage is applied to a common electrode point close to the data driver and far away from the gate driver, the third highest common voltage is applied to a common electrode point far away from the data driver and close to the gate driver, and the lowest common voltage is applied to a common electrode close to both of the data driver and the gate driver.

Liquid crystal display having different common voltages

Thin-film transistor display devices include composite electrodes which provide low resistance contacts and paths for electrical signals and are less susceptible to parasitic metal migration which can limit display quality and lifetime. In particular, a thin-film transistor (TFT) display device is provided having an insulated gate electrode on a face of a substrate (e.g., transparent substrate) and a semiconductor layer on the insulated gate electrode, opposite the face of the substrate. Spaced apart source and drain electrodes are also provided on the semiconductor layer. These source and drain electrodes each preferably comprise a composite of at least two layers containing respective metals therein of different element type. Preferably, one of the layers comprises a metal which is capable of forming a low resistance contact with electrodes such as a pixel electrode (e.g., transparent indium-tin-oxide electrode) and the other of the layers comprises a relatively low resistance metal so that the overall effective resistance of each composite electrode is maintained at a low level.

Thin-film transistor display devices having composite electrodes

A pixel is formed on a substrate for a panel of an LCD display, disposed adjacent a data line. The pixel includes a plurality of spaced apart elongate pixel electrodes extending parallel to the data line and a plurality of spaced apart elongate common electrodes extending parallel to the data line and interspersed among the pixel electrodes such that a respective pixel electrode is disposed adjacent a respective common electrode. The common and pixel electrodes define a plurality of gaps, a respective one of the gaps separating a common electrode and a pixel electrode, the plurality of gaps having nonuniform widths. Preferably, the plurality of gaps includes a first group of gaps having a first width and a second group of gaps having a second width. According to one embodiment, the first group of gaps includes all of the plurality of gaps except a gap between one common electrode nearest the data line and a pixel electrode nearest the one common electrode. According to another embodiment, the first group of gaps includes all of the plurality of gaps except a gap between a first common electrode nearest the data line and a pixel electrode nearest the first common electrode and a gap between a second common electrode furthest from the data line and a pixel electrode nearest the second common electrode.

In-plane switching type liquid crystal display devices having improved aperture ratio and methods of fabrication therefor using nonuniform spacing between pixel and common electrodes

A gate wire including a gate line and a gate electrode and a common signal line are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal line. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer of the gate electrode, a source and a drain electrode thereon and a data line connected to the source electrode on the gate insulating layer are formed. A protection insulating layer is formed on the data line and the source and the drain electrodes. Common electrodes that are connected to the common signal line and pixel electrodes, which are connected to the drain electrode, are formed thereon. An alignment layer, which is in direct contact with the common electrodes and the pixel electrodes, is formed in pixel region where the common electrodes and the pixel electrodes are formed. The thickness of the pixel electrodes and the common electrodes is equal to or less than 1,000 &angst; with a taper angle.

In-plane switching mode liquid crystal display and a method manufacturing the same

Disclosed is a liquid crystal display. The LCD includes an active area realized through a plurality of panel shots and stitch verniers for measuring stitch errors between the panel shots. The LCD is manufactured by forming first, second and third masks, each mask having a mask shot for forming the panel shots and a plurality of vernier patterns provided on a periphery of the mask shots for forming the stitch verniers; exposing the first mask to form a first panel shot in the active area of the LCD and a plurality of stitch verniers on a periphery of the first panel shot; exposing the second mask to form a second panel shot in the active area of the LCD and a plurality of stitch verniers on a periphery of the second panel shot; exposing the third mask to form a third panel shot in the active area of the LCD and expose stitch verniers which are formed on the periphery of the first panel shot and located in an area of the active area corresponding to the third panel shot; and removing the stitch verniers exposed by the third mask and formed in the active area corresponding to the third shot.

Liquid crystal display and a manufacturing method thereof

Flat panel display devices having improved signal line repair capability utilize repair lines which have reduced parasitic capacitance with other active signal lines when connected to provide a repair function. This reduced parasitic capacitance is a result of a reduced number of overlaps between active signal lines (or other repair lines) and each repair line performing a repair function. A main repair line is provided on a display substrate to provide a repair function in the event one of the signal lines is defective. If a repair function is needed because a data line is defective (e.g., 'opened'), this main repair line is electrically connected to a first end of the defective data line and indirectly electrically connected to a second end of the defective data line. The indirect electrical connection is provided by a sub-repair line, which can be electrically connected (i.e., 'shorted') to the main repair line, and a data line extension which is electrically connected to a second end of the defective data line and the sub-repair line. To further reduce parasitic capacitance caused by overlaps between wiring patterns, the main repair line and data line extension are provided at a first wiring level and the data line and sub-repair line are provided at a second wiring level.

Flat panel display devices having improved signal line repair capability

Liquid crystal display panels having control lines with uniforms

A matrix-type display capable of being repaired by pixel unit, Two or more of signal lines such as scanning lines, image signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the image signal lines and scanning lines, the short of the pixel electrode and the signal line, and the loss of electrode of a switching element, and a pixel defect can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Matrix-type display capable of being repaired by pixel unit and a repair

A sampling clock signal recovery device and method for providing the sampling clock signal recovery device, in a receiving terminal of a discrete multitone (DMT) system, for accurately recovering a sampling clock signal by reducing sampling-induced jitter noise, i.e., by removing additive white Gaussian noise (AWGN) from the receiving terminal of the DMT system, and stably recovering a sampling clock signal. The above is accomplished by determining whether the phase error is smaller than a predetermined threshold value. If the phase error is equal to, or greater than the predetermined threshold value, then the instant invention corrects the sampling clock signal by the phase error. However, if the phase error is less than the predetermined threshold value, then the instant invention calculates an average value of some or all of decision error values, and corrects the sampling clock signal by the average value. Thus, a sampling clock signal is more accurately recovered.

Sampling clock signal recovery device and method in receiving terminal

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Kyungki-do, South Korea

Dong-gyu Kim