Samsung Electronics Co., Ltd.

Dong-Gun Park

Choong-Ho Lee

Chang-Woo Oh

Jae-Man Yoon

Jeong-Dong Choe

Shin-Ae Lee

Chang-Sub Lee

Sung-Min Kim

Dong-won Kim

Dong-Won Kim

Chul Ho Lee

Seong-Ho Kim

Seong-goo Kim

Eun-jung Yun

Sung-young Lee

Byung-yong Choi

Bong-Soo Kim

Sung-min Kim

Hyeoung-won Seo

Kang-yoon Lee

Hee-Soo Kang

Seung-bae Park

Tae-Yong Kim

Min-sang Kim

Sung-Young Lee

Hye-Jin Cho

Young-Joon Ahn

Hye-jin Cho

Chang-Hyun Lee

Kyoung-hwan Yeo

Yun-Gi Kim

Sung-Dae Suk

Yong-Kyu Lee

Sung-Hwan Kim

Gyo-young Jin

Eun-Suk Cho

Ming Li

Sang-Yeon Han

Yoon-Dong Park

Suk-Pil Kim

Yang-Kyu Choi

Won-joo Kim

Byung-Yong Choi

Suk-Kang Sung

Young-mi Lee

Won-sok Lee

Makoto Yoshida

Tae Kyung Kim

Joo-Young Lee

Jeong-Hyuk Choi

Jae-Duk Lee

Dong-Uk Choi

Tai-Su Park

Yong-kyu Lee

Jong-woo Park

Hyeoung-Won Seo

Sung-hwan Kim

Young-joon Ahn

Joon-Mo Kwon

Jin-Kee Choi

Hee-soo Kang

Yoshida Makoto

Won Shik Lee

Hyeong-Chan Ko

Hong-Joon Moon

Lee-Eun Yu

Moon-suk Yi

Yeong-taek Lee

Hui-Jung Kim

Hyun-Woo Chung

Jae-woong Hyun

Kang-Uk Kim

Yong-chul Oh

Jae-man Yoon

Keun-Nam Kim

Ju-hyun Kim

Kang-Yoon Lee

Seong-ho Kim

Woun-suck Yang

Woun-Suck Yang

Chang-Hoon Kim

Choong-ho Lee

Jae-Man Youn

Jae-Mun Youn

Jeong-Dong Choi

A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

Recessed transistor and method of manufacturing the same

Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Methods of manufacturing semiconductor devices having a support structure for an active layer pattern

Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

Nonvolatile memory devices having gate structures doped by nitrogen

Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4Fstructure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

Semiconductor memory device having vertical channel transistor and method for fabricating the same

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

Semiconductor devices including fin shaped semiconductor regions and stress inducing layers

A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided.

Semiconductor devices having recessed channels

Semiconductor devices having a support structure for an active layer pattern

A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Field effect transistor and method for manufacturing the same

Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.

Molecular devices and methods of manufacturing the same

Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.

Semiconductor devices and methods of fabricating the same

Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Methods of manufacturing vertical channel semiconductor devices

Methods of forming semiconductor devices having recessed channels

A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.

Method of forming a metal layer pattern having a nanogap and method of manufacturing a molecule-sized device using the same

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Gyeonggi-do, South Korea

Dong-Gun Park