Skhynix Inc.

Samsung Electronics Co., Ltd.

Nexon Corporation

Dong-Gun Kim

Do-Sun Hong

Yong-Ju Kim

Hong-Sik Kim

Yong-Kee Kwon

Won-Moon Cheon

Jung-Hyun Kwon

Sang-Gu Jo

Jong-Won Kim

Seung-Gyu Jeong

Dong-Young Seo

Soeng-hun Kim

Sang-Bum Kim

Dae-Ho Kim

Young-Suk Moon

Kue-Hwan Sihn

Seung-Ri Jin

Je-Young Park

Wei Xia

Hee-Jin Chung

Byung-Soo Moon

Hong-Moon Wang

Pan Yang

A storage system includes a storage device and a host device. The storage device includes a nonvolatile memory device having a first size and a first volatile memory device having a second size smaller than the first size and configured to operate as a cache memory with respect to the nonvolatile memory device. The first volatile memory device is configured to allow a first bus portion access to cache data stored in the first volatile memory device. The host device is configured to generate a cache table corresponding to information in the cache data stored in the first volatile memory device and configured to read the cache data stored in the first volatile memory device via the first bus portion based on the cache table.

Storage system and method of operating the same

Disclosed are a communication technique for merging, with IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system and a system therefor. The present disclosure can be applied to intelligent services (for example, smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail, security and safety-related services, and the like) on the basis of 5G communication technology and IoT-related technology. Disclosed is a method by which a terminal performs a random access, comprising: receiving, from a serving base station, a handover command including configuration information indicating a dedicated random access resource and a common random access resource determining whether to perform a random access by using at least one of the dedicated random access resource and the common random access resource according to predetermined criteria; and performing the random access on the basis of the determination result.

Method and device for performing random access procedure

In a cache memory used for communication between a host and a memory, the cache memory may include a plurality of cache sets, each comprising: a valid bit; N dirty bits; a tag; and N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to a data chunk size of the host, wherein a data chunk size of the memory is N times as large as the data chunk size of the host, where N is an integer greater than or equal to 2.

Cache memory, memory system including the same, and eviction method of cache memory

A computing system includes a host and a storage device. The host includes a central processing unit (CPU) and a first volatile memory device. The storage device includes a second volatile memory device and a nonvolatile memory device. The CPU uses the first volatile memory device and the second volatile memory device as a main memory to store temporary data used for operation of the CPU. The CPU determines a swap-out page to be swapped-out of first pages stored in the first volatile memory device, determines a swap-in page to be swapped-in of second pages stored in the second volatile memory device, and exchanges the swapped-out page and the swapped-in page.

Computing systems and methods of operating computing systems

A method of operating a storage device includes receiving a first logical address from a host, determining whether first metadata stored in a volatile memory of the storage device and associated with the first logical address is corrupted, processing the first metadata as an uncorrectable error when the first metadata is determined to be corrupted, providing an error message to the host indicating that an operation cannot be performed on data associated with the first logical address when the first metadata is processed as the uncorrectable error, after the providing of the error message, receiving a second logical address from the host, determining whether second metadata stored in the volatile memory and associated with the second logical address is corrupted, and performing an operation of accessing the non-volatile memory based on the second metadata, when the second metadata is not determined to be corrupted.

Storage device for processing corrupted metadata and method of operating the same

Provided is a method including acquiring reading and writing information of logical chunks of a storage apparatus in a number of historical periods before a current time, and predicting reading and writing information of the logical chunks in a next period according to reading and writing information of the logical chunks in a number of historical periods before the current time and a data prediction model. The data prediction model indicates a relationship between reading and writing information of the logical chunks in a next period and reading and writing information of the logical chunks in a number of historical periods before the current time.

Storing method and apparatus of data

A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Semiconductor system and method for operating the semiconductor system

A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Memory system and wear-leveling method using the same

A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.

Memory system and operation method thereof

A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.

Memory system and error correcting method thereof

A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.

Memory system and operating method thereof

A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.

Memory system and method for wear-leveling by swapping memory cell groups

A test device includes a data driver and a controller. The controller is configured to generate a test code by dividing a test sequence in a unit of n-bits. The data driver is configured to receive the generated test code and output one of input voltages to a device under test as a test signal based on the generated test code. A storage device stores a test sequence.

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Gyeonggi-do, South Korea

Dong-Gun Kim