Samsung Electronics Co., Ltd.

Dong-Chul Kim

Sun-ae Seo

Hyun-jong Chung

Myoung-jae Lee

In-gyu Baek

Seung-eon Ahn

Ran-ju Jung

Moon-Sook Lee

Yun-sung Woo

Chang-won Lee

Young-soo Park

Eun-hong Lee

In-Kyeong Yoo

Dae-young Jeon

Jong-wan Kim

Jin Seong Heo

Sang-jin Park

Jang-Eun Lee

Jin-seong Heo

Hyo-San Lee

Ji-young Bae

Sun-Ae Seo

Hyeong-jun Kim

Seok-Hoon Kim

Young-Kwan Cha

Sang-Jin Park

Eun-Kyung Yim

Kyoung-Seob Kim

Seung-Eon Ahn

Myoung-Jae Lee

Byoung-Ho Park

In a method of cleaning a substrate, a protecting liquid may be sprayed to a surface of the substrate from a first position in a first spray direction. Cleaning droplets may be injected on to the surface of the substrate. The protecting liquid may be sprayed to the surface of the substrate from a second position different from the first position in a second spray direction. For example, the protecting liquid may be always sprayed from the central portion toward the edge portions in the substrate so that the protecting liquid on the substrate may have a uniform thickness.

Method of cleaning a substrate and apparatus for performing the same

A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Resistive memory cells and devices having asymmetrical contacts

An electronic device, a transparent display and methods for fabricating the same are provided, the electronic device including a first, a second and a third element each formed of a two-dimensional (2D) sheet material. The first, second, and third elements are stacked in a sequential order or in a reverse order. The second element is positioned between the first element and the third element. The second element has an insulator property, the first and third elements have a metal property or a semiconductor property.

Electronic device using a two-dimensional sheet material, transparent display and methods of fabricating the same

The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.

Graphene device and method of manufacturing the same

Provided is an electromechanical switch and a method of manufacturing the same. The electromechanical switch includes an elastic conductive layer that moves by the application of an electric field, wherein the elastic conductive layer includes at least one layer of graphene.

Electromechanical switch and method of manufacturing the same

Example embodiments relate to a resistive random access memory (RRAM) and a method of manufacturing the RRAM. A RRAM according to example embodiments may include a lower electrode, which may be formed on a lower structure (e.g., substrate). A resistive layer may be formed on the lower electrode, wherein the resistive layer may include a transition metal dopant. An upper electrode may be formed on the resistive layer. Accordingly, the transition metal dopant may form a filament in the resistive layer that operates as a current path.

Resistive random access memory and method of manufacturing the same

A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.

Nonvolatile memory device and nonvolatile memory array including the same

A resistive random access memory (RRAM) having a solid solution layer and a method of manufacturing the RRAM are provided. The RRAM includes a lower electrode, a solid solution layer on the lower electrode, a resistive layer on the solid solution layer, and an upper electrode on the resistive layer. The method of manufacturing the RRAM includes forming a lower electrode, forming a solid solution layer on the lower electrode, forming a resistive layer on the solid layer and forming an upper electrode on the resistive layer, wherein the RRAM is formed of a transition metal solid solution.

Resistive random access memory having a solid solution layer and method of manufacturing the same

Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.

Field effect transistor, logic circuit including the same and methods of manufacturing the same

Provided are a stack structure including an epitaxial graphene, a method of forming the stack structure, and an electronic device including the stack structure. The stack structure includes: a Si substrate; an under layer formed on the Si substrate; and at least one epitaxial graphene layer formed on the under layer.

Stack structure comprising epitaxial graphene, method of forming the stack structure, and electronic device comprising the stack structure

Provided is a graphene device and a method of manufacturing the same. The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.

Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines.

Cross-point latch and method of operating the same

A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Growing community of inventors

Suwon-si, South Korea

Dong-Chul Kim