Texas Instruments Corporation

Conexant Systems, Inc.

Dong Cho

John S Walley

Kang Xiao

Joanne Wu

Stephen Finch

Patrick Conley

Mark J Blair

James Schaffner

A typical integrated circuit device may include a central processing unit (CPU), trap and patch (T&P) logic circuits and registers. Volatile RAM and read only memory (ROM) are also provided. A predetermined number of memory locations in the RAM are allocated for defective memory cell replacement. When power is turned on or the system is reset, the CPU executes a program stored in ROM which identifies defective RAM locations on the fly and loads the trap and path circuits and registers with the defective addresses and the replacement or patch RAM locations (addresses). When the CPU reads or writes to the bad RAM locations, the T&P logic inserts the patch address of the good RAM memory location for the reading and writing operations. In this manner, virtual defective RAM replacement is transparent to the CPU.

Trap and patch system for virtual replacement of defective volatile memory cells

The present invention provides a method and apparatus for providing position detection using a unique binary sequence encoded in indexing bits stored in servo wedges. The present invention generates a unique binary sequence (UBS) code and stores the bits of such a code in the indexing bits of the servo wedges. The bits are read from the servo wedges and used to provide unique identification of head position. Each servo wedge and each data field can be uniquely identified, even servo wedges and data fields under different heads. The present invention may be used to provide initial position detection, position verification during normal operation, and position verification upon head switching. When used for position verification, the present invention uses a confidence block to determine the confidence level with which the head is believed to be correctly positioned. One or more programmable thresholds may be used to qualify operations such as reading information from a disk, writing information to a disk, or seeking a location on a disk. If these thresholds are not met for the corresponding operations, the initial position detection capability of the present invention may be used to provide position recovery.

Position detection scheme for headerless disk controller

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Pomona, CA, United States of America

Dong Cho