International Business Machines Corporation

Veeco Instruments Inc.

Bruker Nano Gmbh

Ebay, Incorporated

Rave LLC

Other

Veeco Metrology, Inc.

Wisconsin Alumni Research Foundation

Dong Chen Chen

Kenneth Gilbert Roessler

Alan G Gara

Philip Heidelberger

James Michael Hammond

Edwin Flecha

Mark Edwin Giampapa

Paul William Coteus

Todd Edward Takken

Matthias Augustin Blumrich

Burkhard D Steinmacher-Burow

Pavlos Michael Vranas

Erik Novak

Florin Munteanu

G Lawrence Best

Gerard Vincent Kopcsay

Lawrence Shungwei Mok

Martin Ohmacht

Thomas Mario Cipolla

George L Chiu

Dirk Hoenicke

Shilpa Jois Rao

Gyan Vatsaraja Bhanot

Seyed-Mahdi Pedramrazi

Shaumik Chandra Mondal

Subramanian Sri Sankaran

Bryan Ephraim Freeland

Rita Marion Bosch

James L Grubbs, Jr

Yves Corfield Martin

James A Thomson

Burkhard Steinmacher-Burow

Sameer Kumar

Gheorghe Almasi

Joanna Schmit

Bryan W Guenther

Luis H Ceze

Matthew Jarrod Novak

Daniel Ahn

Son Hoang Bui

Jaime Duran

Sarabjeet Singh

Philip Heidlberger

Henry Fagg

Mark Munch

Mark E Giampap

Gerard V Kopscay

Visual diagram searching techniques are described herein. A visual diagram service enables users to efficiently search for data for item parts even in cases where the name of the item part is unknown. In one or more examples, search query input to locate item parts of an item is received via a user interface displayed by at least one computing device. A visual diagram of the item is displayed in the user interface. The visual diagram includes selectable portions mapped to respective item parts depicted in the corresponding selectable portion of the visual diagram. A user selection of one of the selectable portions of the visual diagram of the item is received via the user interface. In response to the user selection, search result data corresponding to the respective item part depicted in the selected selectable portion of the visual diagram of the item is displayed.

Method, computer readable storage devices, and computer device for mapping visual diagram portions to parts listing information

Visual diagram searching

Side illumination is combined with scanning interferometry to provide a means for measuring with a single data-acquisition scan surfaces that contain sections suitable for interferometric processing as well as sections that are not suitable because of lack of fringes produced by the measurement. In the sections where no fringes are produced, the irradiance detected during the scan is processed using a depth-from-focus mapping method to yield a corresponding measurement. The result is a complete profilometric measurement of the sample surface with a single scan. In addition, by increasing sample irradiance through side illumination, the structural features of the sample become markedly more visible than when illuminated only by the object beam of the interferometer, which greatly facilitates finding focus and identifying regions of interest for the measurement.

Side illumination in interferometry

A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

Multiprocessor system with multiple concurrent modes of execution

A conductive conformable braided wire is used as the edge electrode for material characterization of a semiconductor wafer. The braided wire is adapted to contact the perimeter of the n-GaN layer using a retractable support structure that alternately places the electrode in contact with the edge of the n-GaN layer and retracts it during repeated cycles of operation to test a plurality of similar wafers. The braided wire produced a very stable and higher electrical contact than any prior-art edge electrode.

Edge electrode for characterization of semiconductor wafers

A conductive probe for semiconductor material characterization includes a distal metallic layer of micrometer-size particles, an intermediate layer of conformable conductive elastomer material, and a pin attached to the elastomer layer. The probe is preferably manufactured by filling a recess in a bottom plate with the metallic particles, coupling a top plate thereto with a perforation aligned with the recess, and filling the perforation with uncured conductive elastomer. The pin, preferably spring-loaded, is pressed into the perforation to compress the silicone to its intended probe size. The silicone is then allowed to cure at room temperature or in a heated environment, or both.

Probe and method of manufacture for semiconductor wafer characterization

A diode model and conductive-probe measurements taken at the wafer lever are used to predict the characterization parameters of a semiconductor device manufactured from the wafer. A current-voltage curve (I-V) model that expresses a current-voltage relationship as a function of resistance, ideality factor, and reverse saturation current is fitted to a number of conductive-probe measurement data. The current-voltage curve (I-V) for the device is then estimated by subtracting from the (I-V) model the product of current times the resistance produced by fitting the (I-V) model.

Predicting LED parameters from electroluminescent semiconductor wafer testing

Forward voltage drift in a probe system for the characterization of a light-emitting wafer is virtually eliminated by directing compressed air to the probe so as to ensure that the exact same temperature conditions exist during repeated measurements of the wafer. In one embodiment of the invention, an air flow at room temperature is used, either continuously or intermittently. In another embodiment, the temperature of the probe is controlled by flowing a liquid or a gas through micro-channels built into the probe. In yet another embodiment, the probe is connected to a solid-state Peltier cell that is computer-controlled to maintain the probe's temperature at a predetermined set-point. A temperature-controlled chamber or a thermal reservoir enclosing the probe could be used as well. The results obtained showed remarkable repeatability.

Testing of electroluminescent semiconductor wafers

A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

Store-operate-coherence-on-value

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

Massively parallel supercomputer

A patterned sapphire substrate is measured from a fine phase map and a coarser height map of the sample. The boundaries of the PSS features are identified by finding the locations of minimum contrast in the modulation map of the substrate and are used to produce a height map of the substrate base and a phase map of center regions of the features. A fringe-order map of the features with respect to the base is used to identify the most prevalent fringe order of pixels in the center-regions of the features. That fringe order is adopted as the correct offset between corresponding pixels in the phase map of the center regions of the features and the base of the substrate. A complete map of the substrate is thus obtained by combining the phase map of the features with the height map of the substrate with an offset equal to the fringe order produced by the invention.

Interferometric technique for measuring patterned sapphire substrates

Correction factors for the ALR and PTR parameters of magnetic-head sliders are determined by calculating an effective reflectivity and a corresponding PCOR at each pixel of the air-bearing surface. The absolute value of reflectivity at each pixel of the AlTiC air-bearing surface is obtained from an empirical equation relating it to modulation. The ratio of AlOand TiC in the AlTiC surface is then calculated at every pixel assuming a linear relationship between the absolute value of AlTiC reflectivity and the theoretical reflectivity of each constituent. The linear relationship is then also used to calculate the effective (complex) reflectivity for the AlTiC material from the relative concentrations of AlOand TiC at each pixel.

Interferometric measurement of non-homogeneous multi-material surfaces

The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via 'all-to-all' distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates efficient utilization of the network thereby efficiently implementing the multidimensional FFT. The 'all-to-all' re-distribution of array elements is further efficiently implemented in applications other than the multidimensional FFT on the distributed-memory parallel supercomputer.

Efficient implementation of multidimensional fast fourier transform on a distributed-memory parallel multi-node computer

Growing community of inventors

Croton-on-Hudson, NY, United States of America

Dong Chen Chen