Samsung Electronics Co., Ltd.

Dong-Chan Kim

Myeong-Cheol Kim

Yu-Gyun Shin

Tai-Su Park

Chang-Jin Kang

Seong-Hoon Jeong

Seung-Hwan Lee

Young-wook Park

Kyeong-Koo Chi

Yeong-kwan Kim

Jong-Hoon Kang

Jeong-Do Ryu

Si-Young Choi

Bum-Soo Kim

Jong-Ryeol Yoo

Jae-Ho Min

Je-Woo Han

O-Ik Kwon

Seung-Hoon Choi

Jae-Hwang Sim

Han-jin Lim

Ji-sang Lee

Seung-Pil Chung

Jae-hong Park

Byeong-Yun Nam

Soo-jin Hong

Gyung-Jin Min

Young-Ju Park

Ja-Eung Koo

Yoon Jin Kim

Il-Young Yoon

Jae-ho Min

Chang-Min Choi

Man-Geun Cho

Kwan-Sik Kim

Sang-jeong Oh

Bo-un Yoon

Dong-hyun Kim

Sang-Jin Hyun

Sang-Bom Kang

Chul-Sung Kim

Sung-Il Cho

Su-Jin Ahn

Seok-Woo Nam

Kong-Soo Lee

Dong-Kyu Lee

Byoung-ho Kwon

Eun-ae Chung

Young-Geun Park

Sang-Yeol Kang

Sung-Nam Chang

Mi-suk Huh

Chang-jin Kang

Bong-hyun Kim

Deok-hyung Lee

Kyung-Yub Jeon

Chan-Hoon Park

Sug-Hun Hong

Ju-Eun Kim

Jong-Su Kim

Jun-ho Yoon

Masayuki Tomoyasu

In-Sang Jeon

Sung-Hoon Chung

Bong-Yong Lee

Heung-Sik Park

Wook-Yeol Yi

Yong-Moon Jang

Ki-hyun Park

Ae-Jeong Lee

Jung-Soo An

Moo-Rym Choi

Gun-Joong Lee

Se-il Kim

Jung-Sup Oh

Jung-Geun Park

Choong-seob Shin

Kyeong-Koo Ghi

Chang-Mu An

O-lk Kwon

Ki-Hong Nam

A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

Semiconductor device and method of manufacturing the same

A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.

Non-volatile memory device and program method of a non-volatile memory device

Disclosed is a method of performing, by a first device, short-range wireless communication with a second device, the method including receiving, from the second device, second authentication information encrypted using first authentication information of the first device, decrypting the encrypted second authentication information by using the first authentication information, determining a secret key based on the decrypted second authentication information, and performing communication between the first device and the second device by using the determined secret key.

Method for communication between devices and devices thereof

In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.

Methods of operating nonvolatile memory devices including erasing a sub-block

A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

Memory device, memory system, method of operating memory device, and method of operating memory system

A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Methods of manufacturing semiconductor devices using alignment marks to align layers

A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.

Method for fabricating a semiconductor device

A patterning method using a metal mask includes sequentially forming a lower metal layer and an upper metal layer on an etching object layer, forming an upper metal mask, forming the upper metal mask including patterning the upper metal layer, forming a lower metal mask, forming the lower metal mask including patterning the lower metal layer using the upper metal mask, and patterning the etching object layer using the upper metal mask.

Patterning method using metal mask and method of fabricating semiconductor device including the same patterning method

A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Methods of fabricating memory devices using wet etching and dry etching

A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line.

Semiconductor device

A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer.

Method of fabricating semiconductor device using photo key

A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor

Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Methods of forming fine patterns in semiconductor devices

Growing community of inventors

Seoul, South Korea

Dong-Chan Kim