Skhynix Inc.

Dong-Beom Lee

Tae-Sik Yun

A neuromorphic device according to various embodiments of the present disclosure includes a recognizing unit suitable for recognizing information based on a plurality of learned results to generate a plurality of recognition signals, a maximum value extracting unit suitable for respectively extracting values of the plurality of recognition signals and extracting a recognition signal having a maximum value among the plurality of recognition signals, and a control unit suitable for processing the information based on the recognition signal having the maximum value.

Apparatus and method for recognizing information of neuromorphic device with signal extracting circuits for selecting output nodes corresponding to recognition signal having maximum value

A memory device may include a plurality of first sense amplifiers including a plurality of corresponding first input terminals, a plurality of second sense amplifiers including a plurality of corresponding second input terminals, the plurality of first and second sense amplifiers being suitable for amplifying data received through the respective plurality of first and second input terminals, and for outputting the amplified data which include first and second data outputted by the plurality of first sense amplifiers and third and fourth data outputted by the plurality of second sense amplifiers; a plurality of first pipe latches suitable for latching and outputting the first and second data at a specific interval; a plurality of second pipe latches suitable for latching and outputting the third and fourth data at a specific interval; and an input/output line coupled to the plurality of first and second pipe latches, suitable for outputting the first, second, third and fourth data.

Memory device with sense amplifier groups and pipe latch groups

A multi-chip package includes first and second semiconductor chips that are sequentially stacked, each of the first and second semiconductor chips including an operation block for an internal operation, third and fourth semiconductor chips that are sequentially stacked over the second semiconductor chip and rotated 180 degrees in a horizontal direction with respect to the first and second semiconductor chips, each of the third and fourth semiconductor chips including an operation block, and through chip vias for transmitting predetermined signals between the operation blocks of the first to fourth semiconductor chips.

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Gyeonggi-do, South Korea

Dong-Beom Lee