Stmicroelectronics S.r.l.

Donatella Brambilla

Alberto Salina

Danilo Rimondi

Carolina Selva

Rita Zappa

An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage. Said second logic gate includes a pull-up branch coupled between a terminal for providing the supply voltage and the second output terminal, and a pull-down branch coupled between the second output terminal and a terminal for providing the reference voltage. Said memory device includes variation means adapted to selectively vary a gain factor of at least one between the pull-down branch and the pull-up branch of said first logic gate and second logic gate depending on the operation performed by the reading and writing means.

Adjustable impedance SRAM memory device

In a current mode pulse width modulation (PWM) integrated drive system having an external load, a switched-capacitor amplifier and a sample & hold stage connected in cascade form a current sensing amplifier for a control loop. The current sensing amplifier overcomes resistive mismatchings, thus permitting a scaling down of the supply voltage with high precision for the integrated drive system.

Integrated current mode PWM drive system supply voltage scaleable while retaining a high precision

A mixed mode PWM/Linear driving system for at least one inductive-resistive (L-R) actuator as a function of operating conditions thereof includes a first full bridge power stage including four power switching devices arranged in pairs for being driven in phase opposition. The system also includes a pulse width modulation (PWM) converter for producing a PWM signal directly driving the first full bridge power stage during a PWM mode operating phase. A second full bridge power stage also comprises four power switching devices of different electrical characteristics from the power switching devices of the first full bridge power stage. The system further includes a pair of amplifiers connected to respective pairs of power switching devices of the second full bridge power stage for driving same in phase opposition during a linear mode operating phase. A switch is provided for switching between the PWM mode operating phase and the linear mode operating phase.

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Mariano Comense, Italy

Donatella Brambilla