International Business Machines Corporation

Donall G Bourke

John David Wilson

Richard Allen Kelley

Douglas R Chisholm

Hartmut R Schwermer

Charles B Perkins, Jr

Carl A Malmquist

John M Nelson

Roy Y Liu

Gregory D Float

Richard L Place

Louis Peter Vergari

Richard N Mendelson

Max Abbott Bouknecht

Frederic John Puttlitz

Luis Madruga

In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous 'handshaking' manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

Coupled synchronous-asychronous bus structure for transferring data

Method for performing inter-unit data transfer operations among a

In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

Method for transferring information between main store and input output

Input output interface controller connecting a synchronous bus to an

An I/O controller is provided for transferring data between a host processor and a plurality of I/O devices wherein the host processor generates a transfer command and each of the plurality of I/O devices generates multiple asynchronous service requests for transfer to the host processor. Control circuitry is provided for controlling the transfer of the service requests from the plurality of I/O devices to the host processor. The control circuitry generates a host processor interrupt signal for application to the host processor, such that in response to the host processor interrupt signal, the host processor generates the transfer command to allow the control circuitry to transfer the service requests to the host processor.

Data processor input/output controller

A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

Residual status reporting during chained cycle steal input/output

Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. An additional pair of bit positions are provided with each SR to receive lookahead bits from decoder loading circuits which decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block. During each subsequent address translation, the loaded lookahead bits are outgated while the block address is being read from an SR. The lookahead bits are decoded for selecting the required storage unit component of the main memory, and a translator interface is switched to that unit. The lookahead bits are handled by parallel high-speed circuits which operate faster than the larger translation circuits handling the block address being read from the SR. As a result, the required storage unit is selected before a storage unit cycle is generated by the translator for accessing the addressed block.

Translator lookahead controls

Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A differnt form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machine-derived address key. The maximum extendable size of the memory can substantially exceed the maximum addressing capability of any program, which is determined by the relocatable addressability obtained through any stack of segmentation registers. The maximum extendable size of the main memory is determined by the number of bit positions in the physical block address field in a segmentation register (for addressing a physical block in any of the storage units) concatenated with the number of bit positions needed to address a location in any selected storage block.

Outer and asynchronous storage extension system

Common logic in a peripheral device control unit responds to a serially propagated poll signal from I/O control logic, or channel, along with a coded signal identifying either a poll for a cycle steal request or a poll for an interrupt request having one of several priorities. The poll signal received will be captured or propagated to following control units dependent upon whether the control unit has requested a cycle steal transfer, or has requested an interrupt at the priority level indicated by the coded signal accompanying the poll signal. Proper functioning of poll capture or propagation is possible even though one of the control units is physically removed from the serial chain of control units.

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Boca Raton, FL, United States of America

Donall G Bourke