Adaptive Digital Power, Inc.

Pixim, Incorporated

Tripath Technology, Inc.

Donald Wile

Andrew Wu

Huy X Ngo

Systems and methods are disclosed to control a buck converter with a first switching circuit including a first upper power transistor coupled to a first lower power transistor at a first junction; a second upper power transistor coupled to a second lower power transistor at a second junction; an inductor coupled to the first and second junctions; and a load coupled to the second junction.

Fast transient buck regulator with dynamic charge/discharge capability

Systems and methods are disclosed to control a buck converter by performing adaptive digital pulse width modulation (ADPWM) with a plurality of upper power transistors each uniquely controlled to enable greater than 100% duty cycle for the buck converter and a lower power transistor coupled to the plurality of upper power transistors; and driving an inductor having one end coupled to the lower power transistor and the upper power transistors.

Adaptive digital pulse width modulation generator for buck converters

Systems and methods are disclosed to provide a process independent circuit for measuring output current of low drop out (LDO) regulators as well as buck regulators. The system can also measure the on resistance (RDSon) of the buck power transistors.

Systems and methods to perform integrated power measurement and RDSon measurement

Systems and methods are disclosed to detect current for an output load with an inductor. The system includes a high side power transistor a low side power transistor coupled to the high side power transistor; and a controller coupled to the high and low side power transistors.

Adaptive non-positive inductor current detector (ANPICD)

Systems and methods are disclosed to detect a load current in a power regulator by providing power output through power transistors each having a plurality of dead time periods during break-before-make (BBM) of the power transistors; and measuring the load current of the output power circuit during the dead time period.

Systems and methods for switching supply load current estimation

A current detector for an output load includes a high side power transistor; a low side power transistor coupled to the high side power transistor; and a controller coupled to the high and low side power transistors to provide cycle by cycle control of the conduction of the high and low side power transistors, wherein if the controller detects zero or negative current in the output inductor, using a dead time between when the low side power transistor turns off and before the high side power transistor turns on, the low side power transistor is held off during the entirety of the next switching cycle.

Non-positive inductor current detector for step down switching regulators

Systems and methods are disclosed to detect current for an output load with an inductor. The system includes a high side power transistor a low side power transistor coupled to the high side power transistor; and a controller coupled to the high and low side power transistors to provide cycle by cycle conduction of the low side power transistor, said controller adaptively turning off the low side power transistor when the high and low side power transistors are off and an inductor current is non-positive. Adaptation of the turn off of the low side transistor is based on the time position of the detection of the non-positive inductor current and serves to improve the power efficiency of the system.

A current sense amplifier circuit for detecting a first current includes an input gain stage incorporating a feedback loop, a current mirror, a charge integration stage and a comparator. The first current is coupled to an input node of the input gain stage where the input gain stage operates to maintain the voltage at the input node at a substantially constant level. The current mirror is coupled to mirror the first current into a second current. The charge integration stage is coupled to integrate charge associated with the second current to develop a first voltage. The comparator is coupled to compare the first voltage to a reference level and providing an output signal. The comparator generates an output signal having a first value when the first current exceeds a predetermined threshold level and a second value when the first current is less than the predetermined threshold level.

Current sense amplifier circuit

Circuits and techniques are described for compensating for a first parasitic current corresponding to a first parasitic capacitance associated with a first switch. A second switch is configured substantially the same as the first switch, the second switch having a second parasitic capacitance associated therewith. A current mirror coupled to the second switch generates a compensating current in response to a second parasitic current corresponding to the second parasitic capacitance. The compensating current compensates for at least a portion of the first parasitic current.

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San Jose, CA, United States of America

Donald Wile