The Board of Governors for Higher Education, State of Rhode Island and

Donald W Tufts

Qi Li

A discriminant neural network and a method of training the network are disclosed. The network includes a set of hidden nodes having associated weights, and the number of hidden nodes is minimized by the training method of the invention. The training method includes the steps of 1) loading a training data set and assigning it to a residual data set, 2) computing a vector associated with a first hidden node using the residual data set, 3) projecting training data onto a hyperplane associated with said first hidden node, 4) determining the number and locations of hard-limiter thresholds associated with the first node, and 5) repeating the above for successive hidden nodes after removing satisfied subsets from the training data until all partitioned regions of the input data space are satisfied.

Discriminant neural networks

A signal processing apparatus and method for iteratively determining the inverse Arithmetic Fourier Transform (AFT) of an input signal by converting the input signal, which represents Fourier coefficients of a function that varies in relation to time, space, or other independent variable, into a set of output signals representing the values of a Fourier series associated with the input signal. The signal processing apparatus and method utilize a process in which a data set of samples is used to iteratively compute a set of frequency samples, wherein each computational iteration utilizes error information which is calculated between the initial data and data synthesized using the AFT. The iterative computations converge and provide AFT values at the Farey-fraction arguments which are consistent with values given by a zero-padded Discrete Fourier Transform (DFT), thus obtaining dense frequency domain samples without interpolation or zero-padding.

Signal processing apparatus and method for iteratively determining

Apparatus for producing the Fourier coefficients of a time and/or space-varying input signal utilizes a bank of delay filters whose outputs are selectively connected to the inputs of a bank of accumulating circuit each of which produces one of the desired Fourier coefficients. Each of the delay filters produces an output signal which is the weighted average of one or more samples of the input signal, the samples being equally spaced in time over the period of the input signal. The accumulating circuits, equal in number to the number of harmonics in the desired Fourier series, each produce a weighted sum of the output(s) of selected delay filters which are interconnected with the accumulating circuits in accordance with the so-called Mobius function. The apparatus may employ either general purpose or special purpose digital or analog processing circuits, and is particularly suitable for implementation with VLSI fabrication techniques. Futher circuit simplification may be achieved by preprocessing the input signal into a delta modulated bipolar signal to reduce the number of internal data paths and to permit the signal averaging function to be implemented with a simple up-down counter.

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Greenwich, RI, United States of America

Donald W Tufts