International Business Machines Corporation

Globalfoundries Inc.

Donald W Schmidt

Mark S Farrell

Charles W Gainey, Jr

Jeffrey Paul Kubala

Dan F Greiner

Damian Leo Osisek

Timothy John Slegel

Christian Jacobi

Lisa Cranton Heller

Jonathan D Bradbury

David F Craddock

Thomas Anthony Gregg

Daniel V Rosa

Fadi Y Busaba

Bernd Nerz

Christoph Raisch

Peter Dana Driever

Marco Kraemer

Bernard R Pierce

Jane Helen Bartik

Phil C Yeh

Marcel Mitran

Jerry Wayne Stevens

Bruce Marshall Walk

Bruce C Giamei

Robert R Rogers

Bruce Leroy Beukema

Ronald Edward Fuhs

Patrick M West, Jr

Frank William Brice

Benjamin P Segal

James H Mulder

Martin Recktenwald

Donna N Dillenberger

Gary Stuart Puchkoff

Aditya Nitin Puranik

Rajaram B Krishnamurthy

Richard Louis Arndt

Steven G Glassen

Leslie W Wyman

Richard Loise Arndt

Christian Zoellin

Richard K Errickson

Frank Siegfried Lehnert

Janet R Easton

Constantinos Kassimis

Carl Joseph Parris

Anthony Saporito

Gustav E Sittmann, Iii

Chung-Lung K Shum

Renato John Recio

Bruce H Ratcliff

Stephen R Valley

Arthur James Stagg

Michael D Essenmacher

Michael E Baskey

Andrew P Wack

Harry M Yudenfriend

Gregory Francis Pfister

Gong Su

Michael J Cadigan, Jr

Scot H Rider

Sascha Junghans

Eugene P Hefferon

Peter Jeremy Relson

Ugochukwu Charles Njoku

Allan Samuel Meritt

Greg A Dyck

Dale Francis Riedy, Jr

Daniel Francis Casper

Matthias Klein

Charles Franklin Webb

Jeffrey Mark Nick

Hong Min

Parijat Dube

Erwin F Pfeffer

Sameh W Asaad

Rajesh Ramkrishna Bordawekar

Ian David Judd

Jaya Srikrishnan

Michael G Fitzpatrick

Bharat Sukhwani

Mathew S Thoennes

Howard M Haynie

Michael Wayne Brown

Anthony Thomas Sofia

David Arlen Elko

Elpida Tzortzatos

Kenneth J Oakes

Eric N Lais

Ute Gaertner

Robert Francis Berry

David Francis Bacon

John C Dayka

Richard P Tarcza

Jeffrey M Turner

John Scott Houston

Mark A Nelson

Tan Lu

Brenton F Belmar

Storage accesses for merge operations are minimized. A plurality of records of a plurality of input lists are merged. The merging includes determining that an input list of the plurality of input lists has become empty, and checking, based on determining that the input list has become empty, a control specific for the input list. The control is used to determine how to proceed, such as whether to end merging or continue merging.

Controlling storage accesses for merge operations

A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

Directed interrupt virtualization with fallback

An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Directed interrupt for multilevel virtualization

An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt virtualization with running indicator

An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt for multilevel virtualization with interrupt table

An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.

Directed interrupt virtualization with interrupt table

Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.

Temporarily suppressing processing of a restrained storage operand request

An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

Interrupt signaling for directed interrupt virtualization

Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Saving and restoring machine state between multiple executions of an instruction

An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt virtualization

An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.

A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

Sort and merge instruction for a general-purpose processor

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Stone Ridge, NY, United States of America

Donald W Schmidt