Advanced Micro Devices Corporation

Intel Corporation

Donald W McCauley

Bryan P Black

John P DeVale

Edward A Brekelbaum

Jeffrey P Rupley, Ii

Stephen Patrick Thompson

Mohammed Hasan Taufique

Derwin Jallice

Gabriel H Loh

Benjamin Charles Serebrin

Randy B Osborne

Srilatha Manne

William Evan Jones, Iii

Paul S Keltcher

Hemant G Rotithor

Murali M Annavaram

Nitya Ranganathan

A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.

Data cache region prefetcher

The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.

Data cache prefetch hints

A method and apparatus for controlling the aggressiveness of a prefetcher based on thrash events is presented. An aggressiveness of a prefetcher for a cache is controlled based upon a number of thrashed cache lines that are replaced by a prefetched cache line and subsequently written back into the cache before the prefetched cache line has been accessed.

Controlling prefetch aggressiveness based on thrash events

The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.

Data cache prefetch throttle

One or more lines of a cache are prefetched according to a first prefetch routine while training a prefetcher to prefetch one or more lines of the cache according to a second prefetch routine. In response to determining that the prefetcher has been trained, one or more lines of the cache may be prefetched according to the second prefetch routine.

Multimode prefetcher

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Memory array on more than one die

In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor.

Guest interrupt controllers for each processor to aid interrupt virtualization

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.

Prefetching from dynamic random access memory to a static random access memory

A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.

Growing community of inventors

Lakeway, TX, United States of America

Donald W McCauley