Unisys Corporation

Sperry Corporation

Donald W Mackenthun

Mitchell A Bauman

Donald C Englin

Larry L Byers

Kelvin S Vartti

Ferris T Price, Deceased

James H Scheuneman

Gregory B Wiedenman

Gary J Lucas

James L Federici

Gerald J Maciona

Scott D Schaber

Gary D Burns

Dale K Seppa

Jeff A Engel

Nguyen Thai Tran

Joseph H Meyer

Philip J Fye

Michael Allen Fahland

A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP requests. To accomplish this, the system memory bus is provided separate and independent paths to the level two cache and tag memories. Therefore, SNOOP requests are permitted to directly access the tag memories without reference to the cache memory. Secondly, the SNOOP requests are given a higher priority than operations associated with local processor data requests. Though this may slow down the local processor, the remote processors have less wait time for SNOOP operations improving overall system performance.

Method for avoiding delays during snoop requests

Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning.

Method and apparatus for parallel store-in second level caching

An improved directory-based, hierarchical memory system is disclosed that is capable of simultaneously processing multiple ownership requests initiated by a processor that is coupled to the memory. An ownership request is initiated on behalf of a processor to obtain an exclusive copy of memory data that may then be modified by the processor. In the data processing system of the preferred embodiment, multiple processors are each coupled to a respective cache memory. These cache memories are further coupled to a hierarchical memory structure including a main memory and one or more additional intermediate levels of cache memory. As is known in the art, copies of addressable portions of the main memory may reside in one or more of the cache memories within the hierarchical memory system. A memory directory records the location and status of each addressable portion of memory so that coherency may be maintained. Prior to updating an addressable portion of memory in a respectively coupled cache, a processor must acquire an exclusively &ldquo;owned&rdquo; copy of the requested memory portion from the hierarchical memory. This is accomplished by issuing a request for ownership to the hierarchical memory. Return of ownership may impose memory latency for write requests. To reduce this latency, the current invention allows multiple requests for ownership to be initiated by a processor simultaneously. In the preferred embodiment, write request logic receives two pending write requests from a processor. For each request that is associated with an addressable memory location that is not yet owned by the processor, an associated ownership request is issued to the hierarchical memory. The requests are not processed in the respective cache memory until after the associated ownership grant is returned from the hierarchical memory system. Because ownership is not necessarily granted by the hierarchical memory in the order ownership requests are issued, control logic is provided to ensure that a local cache processes all write requests in time-order so that memory consistency is maintained. According to another aspect of the invention, read request logic is provided to allow a memory read request to by-pass all pending write requests previously issued by the same processor. In this manner, read operations are not affected by delays associated with ownership requests.

Cache control system for performing multiple outstanding ownership requests

Flush apparatus for a dual multi-processing system. Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning. The flush apparatus prevents the loss of system data during such a process due to the inherent nature of a store in second level cache.

Method of and apparatus for store-in second level cache flush

An improved conflict detection system for use in maintaining memory coherency in a multiprocessor, shared-cache memory system. The system includes a queue for storing pointers to request addresses that resulted in cache misses. The addresses associated with the queued pointers will generally be presented to a main memory for processing based on a predetermined priority scheme. The system further includes conflict detection logic which uses the queue pointers and the request addresses provided by associated ones of the processors to determine if any two of the queued requests are associated with the same request address. If so, a conflict exists, and the request queue later in time must be re-directed to cache instead of being presented to main memory to maintain cache coherency. The system further includes a mechanism for using pointers to detect conflict situations associated with flush and replacement cache operations. Because the conflict detection system queues pointers to addresses, instead of the addresses themselves, a large amount of silicon area can be saved. In addition, the system performs all conflict detection operations using full address compares to eliminate the detection of false conflicts.

Address conflict detection system employing address indirection for use

A system and method for monitoring and collecting performance characteristics of a target system and providing the results by way of time-division multiplexing is provided. The performance monitor includes a mechanism for latching a plurality of performance attribute signals. An output circuit, coupled to the latching mechanism, is used to output the latched performance attribute signals in groups, wherein each of the groups is a subset of all of the performance attribute signals. The performance monitor further includes a time division circuit coupled to the output circuit, to allow the output circuit to output each of the groups of performance attribute signals at different times. Each group of performance attribute signals can therefore be transmitted via common output access points, although at different times as the groups are transmitted in succession.

Computer performance monitoring using time-division multiplexing

Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.

Second level cache having instruction cache parity error control

A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.

Architecture for smart control of bi-directional transfer of data

A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.

VLSI embedded RAM test

A computer architecture for providing enhanced reliability while mitigating the high costs of total redundancy. The HUB and Street architecture couples a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures and deliver said data to a desired destination. The system designer can either increase or decrease the number of HUB elements and streets to either increase or decrease the reliability and cost of the particular computer system. In addition, the HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. Finally, the HUB elements have the capability of automatically detecting faults within the system and can redirect the data around said faults. This automatic rerouting capability is the subject of the present invention.

Method and apparatus for automatically routing around faults within an

An improved partially duplicated stack structure for ensuring data integrity through a pipelined stack is described. An improved virtual first-in first-out stack structure having a plurality of parallel stacks, each for storing predetermined segments of data signals from a total data word is described in conjunction with one or more associated compare stack structures which are commonly accessed during loading and reading the stack. The compare stack is arranged for storing predetermined selected bit groupings associated with each of the segments of data signals. The bit groupings from the compare stack are compared with like-situated bit groupings from the associated segments of data signals at readout. Failure of the bit-by-bit comparison results in an indication that a stack address decode error has occurred, thereby providing through-checking of the integrity of the functioning of the stack structures.

Partial duplication of pipelined stack with data integrity checking

An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.

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Fridley, MN, United States of America

Donald W Mackenthun