Intrinsity, Inc.

Apple Inc.

Donald W Glowka

James S Blomgren

Stephen C Horne

Jeffrey B Reed

Gopal Vijayan

Robert D Kenney

Paul K Miller

Raymond Cheung Yeung

Timothy A Olson

Thomas W Rudwick, Iii

A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances.

Method for manipulating and repartitioning a hierarchical integrated circuit design

The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.

Physical realization of dynamic logic using parameterized tile partitioning

This invention discloses a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool includes a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool . The routing rule generation tool further includes a noise sensitivity/gate characterization tool and a rule generator tool . The block build tool further includes a gate sizing tool , a gate analysis tool , a route rule selecting tool , a route assigning tool

Generation of route rules

The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer , a levelizer , a backward logic scanner , a forward logic scanner , a gate target delay incrementor , and a gate target delay comparator that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Method for calculating dynamic logic block propagation delay targets using time borrowing

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Austin, TX, United States of America

Donald W Glowka