Ltx Corporation

Sequence Design, Inc.

Other

Inovys Corporation

Donald Vick Organ

Mark E Deome

Wei Ey Li

Phillip D Burlison

Robert G Mathews

Tommie Edward Berry

Christopher Joel Hannaford

David W Curry

David Menis

Eric H Rosenfeld

Edward J Terrenzi

Kenneth J Lanier

Roger W Blethen

H Neil Kelly

Jeffrey H Perkins

Douglas Kaufman

Hazem Almusa

Vinay Srinivas

Larry Ke

Japinder Singh

Michael Carlyle Davis

Richard C Dokken

Michael Gordon Davis

Val N Greene

Rajaneekara Techasaratoole

In one embodiment, a reflecting surface, a gnomon and a dial are arranged so that rays from the sun are reflected toward gnomon such that its projected image is visible on dial. The projected image moves across the dial in response to the movement of sun across the sky, thus providing some indication of time and season. Other embodiments are described and shown.

Reflecting sundial

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, 'hot spots' in the physical design are identified for local transformation using a 'bidirectional combinational total negative slack' (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

Method and apparatus for interconnect-driven optimization of integrated circuit design

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

A method and system for automated multisite testing. Specifically, in one embodiment, a method is disclosed for determining a testing order of plurality of testing operations of a test flow in a multisite testing environment. The method begins by automatically walking through the test flow by performing recursion on the plurality of testing operations. Next, the method automatically assigns a plurality of relative priorities to the plurality of testing operations. The plurality of relative priorities determine the testing order used when executing each of the plurality of testing operations in said test flow. Each of the plurality of testing operations is executed only once when testing a plurality of devices under test (DUTs) in the multisite testing environment.

Method and system for automatically determining a testing order when executing a test flow

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, &ldquo;hot spots&rdquo; in the physical design are identified for local transformation using a &ldquo;bidirectional combinational total negative slack&rdquo; (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

An automated test system that has analog and digital resources for testing mixed signal ICs. A control pattern is provided that is used by the automated test system to simultaneously control both the digital resources and the analog resources. The control pattern is comprised of a sequentially executed two-dimensional array with columns corresponding to analog and digital resources. The automated test system uses the control pattern to control both the analog and digital resources.

Generating and controlling analog and digital signals on a mixed signal test system

A software tool for analyzing the real-time performance characteristics of computer programs. A subprogram automatically records the execution time at a large number of pre-identified points in the code to be analyzed. This time information is captured in real-time and is minimally invasive. The display is subsequently displayed using a timing diagram display tool for a graphical user interface. The displayed timing diagrams provides a visual representation of the execution of the software in time, and provides a user to scale the time or show the profile in an alternate perspective. The present invention further provides a graphical representation of the hierarchical execution of subroutines and program modules within the software by displaying the nested execution of the software.

Capturing and displaying computer program execution timing

Growing community of inventors

Saratoga, CA, United States of America

Donald Vick Organ