Agere Systems Inc.

Agere Systems Guardian Corp.

Lucent Technologies Inc.

Donald Thomas Cwynar

Seungmoo Choi

Timothy Edward Doyle

Sudhanshu Misra

Vivek Saxena

Scott Francis Shive

John Michael Sharpe

Felix Llevada

Dennis Okumu Ouma

Alan Sangone Chen

Troy A Giniecki

A halo implant ( ) for an MOS transistor ( ) is formed in a semiconductor substrate ( ) at a shallow implant angle, relative to normal to the substrate surface ( ). A polysilicon gate structure ( ) is formed over a gate oxide ( ) and then a hard mask ( ), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface ( ) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask ( ). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

Method for fabricating MOS device with halo implanted region

A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout regions overlying the semiconductor substrate. Each layout region will comprise an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacturing. Each dummy fill region in each layout region will have a different density with respect to other dummy fill regions in other layout regions, so that the combined density of the active interconnect feature region and the dummy fill feature region in a layout region will be substantially uniform with respect to a similar combined density in each of the other layout regions.

Semiconductor device having an interconnect layer with a plurality of layout regions having substantially uniform densities of active interconnects and dummy fills

A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.

Method for making an interconnect layer and a semiconductor device including the same

A method of manufacturing a semiconductor device using shallow trench isolation is provided, wherein a plurality of protrusions are formed in the exposed surface of the mask layer overlying the active area of the device. The protrusions are preferably formed by forming a photo-resist layer on the surface of the mask layer and patterning the photo-resist layer such that the photo-resist layer defines a plurality of protrusion areas and a depression area within the defined active area. A portion of the mask layer is removed in the defined depression area to form a plurality of protrusions in the mask layer. Thereafter, a dielectric layer is deposited on the exposed surface of the mask layer and in the shallow trench and evenly planarized.

Shallow trench isolation method

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Orlando, FL, United States of America

Donald Thomas Cwynar