Texas Instruments Corporation

Donald S Miles

Jiong-Ping Lu

Lance Stanford Robertson

Duofeng Yue

Amitabh Jain

Douglas Ticknor Grider

Lindsey H Hall

P R Chidambaram

Amitava Chatterjee

Brian Keith Kirkpatrick

Kaiping Liu

Srinivasan Chakravarthi

Song Zhao

Sue E Crank

Andrew McKerrow

Majid Movahed Mansoori

Clint Montgomery

Clinton L Montgomery

Juanita DeLoach

Ralf B Willecke

Melissa M Hewson

Glenn J Tessmer

Xiaozhan Liu

Chidi P R Chidambaram

Thomas D Bonifiield

Lu Jiong-Ping

Andrew J Mckerrow

The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes forming fluorine containing regions () in the source/drain regions () employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer () over the substrate () and fluorine containing regions (), and reacting the metal layer () with the fluorine containing regions () to form metal silicide regions () in the source/drain regions ().

Method for manufacturing a semiconductor device containing metal silicide regions

The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device () , among other steps, includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes subjecting the gate structure () and substrate () to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains () subsequent to subjecting the gate structure () and substrate () to the dry etch process. Thereafter, the method includes forming metal silicide regions () in the gate structure () and the fluorinated source/drains ().

Method for manufacturing a semiconductor device having silicided regions

A silicideis formed in exposed silicon on a semiconductor waferby a method that includes forming a thin interface layerover the semiconductor waferand performing a first low temperature anneal to create the silicideThe method further includes removing an unreacted portion of the interface layerand performing a second low temperature anneal to complete the formation of a low resistance silicide

Silicide formation using a low temperature anneal process

Fluorine containing regions () are formed in the source and drain regions () of the MOS transistor. A metal layer () is formed over the fluorine containing regions () and the source and drain regions (). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Integrated circuit metal silicide method

A method for forming metal silicide regions in source and drain regions () is described. Prior to the thermal annealing of the source and drain regions (), germanium is implanted into a semiconductor substrate adjacent to sidewall structures () formed adjacent gate structures (). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (). Following thermal annealing of the source and drain regions (), the implanted germanium prevents the formation of metal silicide spikes.

Silicide method for CMOS integrated circuits

A method of reducing dopant losses is provided. The method includes providing a transistor structure having a first region, implanting a dopant into the first region, depositing a control layer adjacent the first region, and performing a first annealing process on the transistor structure. The control layer is operable to prevent at least a portion of the dopant in the first region from diffusing out of the first region toward the control layer during the first annealing process.

Reducing dopant losses during annealing processes

A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel suicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500&deg; C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.

Nickel silicide&mdash;silicon nitride adhesion through surface passivation

Semiconductor device fabrication methods are provided in which a carbon-containing region is formed in a wafer to inhibit diffusion of dopants during fabrication. Front-end thermal processing operations, such as oxidation and/or anneal processes, are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or mitigate dopant diffusion.

Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions

An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that provide side wall spacers of poly oxide and/or cap oxide from the PMOS gate areas before doing PMOS implanting steps(K and M). The capping of the wafer (step G)with the cap oxide after the NMOS implant also prevents the arsenic from out diffusing from the silicon. Further embodiments include implanting directly on the base.

Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates

An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without an oxide layer (step D ), covering the gates with a cap oxide layer(step E ), covering NMOS devices with photoresist(step F ), dry etching all PMOS devices (Step G ), and implanting PMOS devices (step I ).

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Plano, TX, United States of America

Donald S Miles