Microchip Technology Inc.

Arizona State University

Donald S Gerber

Kent D Hewitt

Jeffrey A Shields

Randy L Yach

Gianpaolo Spadini

George N Maracas

Neil F Deutscher

Robert P Ma

Ronald A Ruechner

David M Davies

A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor

A merged two transistor memory cell of an EEPROM, and method of fabricating same, is provided. The memory cell includes a substrate and insulating layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes an ONO stack film that is disposed between the floating gate and the shared gate. In fabricating the memory, the ONO stack film is formed adjacent to the top and side surfaces of the floating gate. The ONO stack film is also formed so as not to be interposed between a potion of the shared gate that is adjacent to the substrate and the insulating layer.

Memory cell having an ONO film with an ONO sidewall and method of fabricating same

A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.

Programming method for a memory cell

A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.

Method for minimizing program disturb in a memory cell

Means and methods for obtaining the separation of large area semiconductor pitaxial device layers from the substrates on which they are grown, the transfer of the grown epi layers to a new host substrate for mounted alignment with features of the new host, and reuse of the original substrate.

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Scottsdale, AZ, United States of America

Donald S Gerber