Altera Corporation

Donald S Fritz

Wen-chou Vincent Wang

Yuan Hang Li

Eng C Cheah

A thermally enhanced wirebond BGA package having a laminate substrate, an IC device mounted on the substrate, and a metal cap defining a cavity inside the package between the IC device and the metal cap. A substantial portion of the cavity is filled with a thermally enhanced epoxy encapsulant establishing a thermal conduction path between the IC device and the metal cap. The BGA package may be further enhanced by bonding a metal heat slug on the laminate substrate and mounting the IC device on the slug.

Thermally enhanced metal capped BGA package

Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate

A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 26 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A stress inhibiting intermediate mounting substrate is connected to the chip carrier through a first array of solder connections. The stress inhibiting intermediate mounting substrate has a second coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the chip carrier and smaller than or equal to the coefficient of thermal expansion of the printed circuit board. Alternate preferred inventive embodiments allow for the cleaning and removal of residual flux and other debris in packaging.

Semiconductor package with stress inhibiting intermediate mounting substrate

An integrated circuit package in which the lead fingers are spaced away from the heat slug is provided. This allows the area of the heat slug to be used for a metallized contact area to serve as a power plane, ground plane, signal bus or the like. The metallized area is preferably insulated from the slug by a ceramic layer. The ceramic layer is preferably adhered to the slug by a nonconductive adhesive, and the metallized layer is preferably a sheet of metal that is preferably adhered to the ceramic layer by a preferably nonconductive adhesive. Nonconductive adhesive can also be used in place of the ceramic layer as an insulating layer. The package preferably also includes an interposer in the windowframe formed around the die by the ceramic layer, with the interposer adhered to the slug by a preferably nonconductive adhesive. More than one interposer, and more than one metallized layer or area, may also be provided.

Integrated circuit package

A leadframe integrated circuit package is provide with an interposer structure for electrically interconnecting a die with the leadframe. The interposer has a rigid substrate, which is mounted in the leadframe in place of a conventional integrated circuit die. Interposer bonding pads at the periphery of the substrate are connected to bond fingers of the leadframe, e.g., by wire bonding. The interposer bonding pads are electrically connected to the die using a network of routing lines connected to a central array of interposer array pads. The array of interposer array pads is connected to a corresponding array of die array pads on the die using metal bumps.

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San Jose, CA, United States of America

Donald S Fritz