General Instrument Corporation

Microchip Technology Inc.

General Instrument Corporation of Delaware

Donald S Butler

Richard S Amano

A two dimensional video convolver generates visually acceptable images on a standard television receiver and includes first and second adder stages and two pixel time period delays. The first adder stage simultaneously receives binary data from three adjacent pixels in a predetermined line in a first direction of a picture to be reproduced on a display during each pixel scan period. The binary data of each of three pixels is processed with a predetermined weight to generate a binary first stage output signal representative of a weighted sum of the plurality of the three pixels in the predetermined line. The second adder stage is responsive to the binary first adder stage output signal during a time period for each of three predetermined adjacent lines in a second orthogonal direction of a picture to be reproduced on a display. The second adder stage processes the binary weighted sum of each of the three lines with a predetermined weight to generate a video convolver output signal representative of a weighted sum of the three pixels in a first direction over three adjacent lines in a second orthogonal direction. Weighting is accomplished in the first and second adder stages by using binary data bits for a pixel as received when the weight for that pixel is a numerical one, and by shifting the received binary data bits by a predetermined number of y bits in a first direction to provide a multiply function when a respective weight is greater than one and equals 2.sup.y.

Method and apparatus for performing two dimensional video convolving

Video magnification apparatus modifies (shrinks or enlarges) video graphic images in a horizontal and vertical direction during a transfer of video graphics data signals from a graphics memory to a television screen. A first magnification modifying device modifies the magnification of a graphic by a vertical magnification factor by generating graphic line address output signals that selectively prevent a transmission of predetermined horizontal lines of the graphic upon the reception of a vertical magnification factor that is less than unity. The first device also causes a transmission of predetermined horizontal lines of the graphic to be selectively repeated upon the reception of a vertical magnification factor that is greater than unity. A second magnification modifying device is responsive to the transmissions of the horizontal lines of the graphic indicated for transmission by the output signals of the first magnification modifying means for modifying the magnification of the graphic in a horizontal direction by a horizontal magnification factor. The second magnification modifying device selects N predetermined pixels of each received X pixel group that are multiplexed into a transmitting X pixel group for transmission in each output signal of the apparatus for a magnification factor equal to or less than unity. Still further, the second device repeats pixels of each received X pixel group a number of times corresponding to an integer magnification factor that is greater than unity for transmission in each output signal of the apparatus.

Apparatus for changing the magnification of video graphics prior to

Apparatus for processing mixed video and graphic signals for display on a television receiver includes a Graphics Memory and a Memory Controller and Sprite State Machine. The Graphics Memory includes a Sprite List table, a Sprite Data table, and other optional tables. The Sprite List table lists one or more graphics in a predetermined sequence for display on the television receiver, and stores general information related to the graphics within control words in each listing. The Sprite Data table stores pixel data for horizontal lines of each of the graphics which are accessed by a control word in each of the graphic listings in the Sprite List table. An optional Line Control table contains control words that are accessed via the graphic listing for providing independent controls for each of the horizontal lines obtained from the Sprite Data table to produce predetermined special effects. An optional Span List table is used to determine which of the graphic listings occur on a horizontal line to cause an accessing of only those occurring graphic listings for assembling pixel data for that horizontal line. The Memory Controller and Sprite State Machine accesses the tables of the Graphics Memory in a predetermined sequence in order to assemble and display each of the graphics and their special effects at predetermined locations in the horizontal lines on a screen of the television receiver. The Memory Controller and Sprite State Machine also uses field enable controls from the Sprite List Table for assembling one graphic on lines of a first filed and a second graphic on lines of a second field.

Apparatus using memory control tables related to video graphics

Apparatus processes mixed YUV and color palettized video signals for display on an interlaced NTSC or television receiver by storing first and second fields of one or more sprites in a graphic memory. Each sprite is stored as YUV or color palettized data and given a priority. A higher priority sprite overwrites pixel data of sprites of a lower priority when sprites overlap. First and second adjacent horizontal lines of pixel data in the first and second fields, respectively, are concurrently stored in respective first and second double buffers of a pixel assembly buffer during each line period. A delay buffer and the first and second double buffers generate first, second, and third adjacent horizontal lines, respectively, of pixel data at the output of the pixel assembly buffer while third and fourth adjacent horizontal lines of pixel data are inputted to the first and second double buffers. A convolving means receives the first, second, and third output signals from the pixel assembly buffer and generates therefrom an output signal providing a weighted average for a central pixel of a predetermined matrix of pixel data for transmission to the television receiver when a sprite is included in a pixel area of the television receiver. A live video signal is transmitted to the display of the television receiver when no sprite is included in a pixel area of the television receiver.

Apparatus for processing mixed YUV and color palettized video signals

A memory system includes a memory array of cells arranged in 'r' rows and 'c' columns, with each row of cells connected to a write conductor and to a separate read conductor. The memory array may be simultaneously written into and read from by a write address decoder having 'r' outputs, one output connected to and corresponding to each write conductor and a read address decoder having 'r' outputs, one output connected to and corresponding to each read conductor. Control signals are applied to the write address decoder to cause the outputs of the write address decoder to scan the memory array at a first rate, in sequence, in a first direction, and control signals are applied to the read address decoder to cause the outputs of the read address decoder to scan the memory array at a second rate, in sequence, in a second direction, opposite the first direction. The first and second rates and the number of rows of the memory array are selected such that no memory location is written into and read from during the same time interval, preventing interference between the read and write functions.

Random access memory with circuitry for concurrently and sequentially

A system for backing up volatile memory such as DRAM with non-volatile memory such as EEPROM includes a volatile memory having refresh logic for cycling through the volatile memory address locations and refreshing the contents thereof, and a non-volatile memory having write logic for writing data into an address location of the non-volatile memory over a write cycle. Each of the volatile and non-volatile memories has its own address bus, and the address buses are connected together for reading out the contents of corresponding address locations of the two memories in the same sequence according to the cycle dictated by the volatile memory refresh logic. The contents read out of each corresponding pair of address locations of the volatile and non-volatile memories are compared in the sequence, and if a difference is detected between the compared contents the address buses are disconnected and a write cycle of the non-volatile memory is initiated to transfer data representing the contents of the address location of the volatile memory found to differ into the corresponding address location of the non-volatile memory.

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Scottsdale, AZ, United States of America

Donald S Butler