Marvell International Limited

Marvellworld Trade Ltd.

Nxp B.v.

Marvell Israel (misl) Ltd.

Marvell Asia Pte., Ltd.

Fairchild Semiconductor Corporation

Marvell Semiconductor Israel Ltd.

Icube Corp.

Sierra Semiconductor

Radlan Computer Communications, Ltd

Donald Robert Pannell

Hong Yu Chou

Hugh Walsh

Maxim Mondaeev

Yosef Meyouhas

Ramya Krishna Devineni

Samuel Kong

Sehat Sutardja

William Lo

Winston Lee

Peter Wang

Tsahi Daniel

Nafea Bishara

Tal Mizrahi

David Melman

Yuval Cohen

Yiqing Guo

Ilan Yerushalmi

Partho Pratim Mishra

Raghu R Kondapalli

Ozdal Barkan

Christian Herber

Philip Axer

Robert Donald Hemming

Raja Banerjea

Paul Aerick Lambert

Mao Yu

Ken Kinwah Ho

Sujan Pandey

Martin Leslie White

Bernd Uwe Gerhard Elend

Fei Wu

Ken Yeung

Abhijit Kumar Deb

Biing Long Shu

Manfred Kunz

Dehuan Meng

Rainer Evers

Steffen Mueller

Claude Robert Gauthier

Weiwen Zhu

Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.

Packet processing system with energy saving features

A switching system comprises a controlling switch and a plurality of port extenders. One of the port extenders includes: at least one upstream port; multiple downstream ports; and a forwarding engine. A forwarding database is populated with entries indicating associations between i) respective network addresses corresponding to devices coupled to downstream ports, and ii) respective local downstream ports. The forwarding database excludes entries corresponding to network addresses corresponding to devices coupled to the at least one upstream port. The forwarding engine is configured to: for a first packet received via one of the local downstream ports, and having a destination network address in the forwarding database, forward the first packet to a different local downstream port indicated by the forwarding database. For a second packet received via one of the local downstream ports, and having a destination network address not in the forwarding database, forward the second packet to the at least one upstream port.

Port extender with local switching

Embodiments of a device and method are disclosed. In an embodiment, an Ethernet communications device includes a physical layer (PHY) unit or a media access control (MAC) unit configured to perform media access control for the Ethernet communications device. The Ethernet communications device includes a security unit configured to manipulate a data stream in a data path within the Ethernet communications device when the data stream violates or conforms to a pre-defined policy.

Ethernet communications device and method for operating an ethernet communications device

Embodiments of a method and device are disclosed. In an embodiment, a method for synchronizing a slave clock in a Time Sensitive Network (TSN) that includes multiple Precision Time Protocol (PTP) clock domains is disclosed. The method involves determining parameters related to multiple PTP clock domains, assigning domain-specific weights to the multiple PTP clock domains based on the determined parameters, generating a control signal for a clock parameter using the domain-specific weights assigned to the multiple PTP clock domains, and adjusting the clock parameter of a slave clock in response to the control signal.

Method and system for merging clocks from multiple precision time protocol (PTP) clock domains

A network switch is disclosed. The network switch includes an input port and an output port. The network switch further includes a rule logic and a memory for storing a configurable counter. The rule logic is configured to inspect a packet received via the input port and attempt to find a rule for the packet and if the rule is found, to reset the counter and process the packet according to a preconfigured follow up action associated with the rule and if the rule is not found, to route the packet according to a default rule. The rule logic is configured to identify the packet for a follow up action based at least on a subset of content of the packet including a header and a payload of the packet. The counter may hold a time value or the number of packets from a same source to a same destination, a number of bytes received from the same source to a same destination, or a user configurable parameter to control the rule validity period.

Network switch

A priority queue sorting system including a priority queue and a message storage. The priority queue includes multiple priority blocks that are cascaded in order from a lowest priority block to a highest priority block. Each priority block includes a register block storing an address and an identifier, compare circuitry that compares a new identifier with the stored identifier for determining relative priority, and select circuitry that determines whether to keep or shift and replace the stored address and identifier within the priority queue based on the relative priority. The message storage stores message payloads, each pointed to by a corresponding stored address of a corresponding priority block. Each priority block contains its own compare and select circuitry and determines a keep, shift, or store operation. Thus, sorting is independent of the length of the priority queue thereby achieving deterministic sorting latency that is independent of the queue length.

Priority queue sorting system and method with deterministic and bounded latency

A proxy slave in a first LIN partition receives data from a proxy master in the second LIN partition which in turn receives the data from a slave in the second LIN partition. The proxy slave stores the data in a data structure and receives a read request from an originating master in the first LIN partition after the data is stored. The read request comprises a LIN message identifier subscribed to by the slave in the second LIN partition. The proxy slave accesses the data stored in the data structure based on the LIN message identifier in the read request; and sends a LIN response to the originating master with the stored data from the slave in the second LIN partition.

Local interconnect network (LIN) messaging between LIN partitions separated by a backbone communication network

Embodiments of a device and method are disclosed. In an embodiment, a physical layer (PHY) device that is compatible with the IEEE 802.3 standard and that utilizes carrier-sense multiple access with collision detection (CSMA/CD) for media access control to a shared media is disclosed. The PHY device includes a physical coding sublayer transmitter (PCS-TX), a physical medium attachment transmitter (PMA-TX), a physical coding sublayer receiver (PCS-RX), a physical medium attachment receiver (PMA-RX), and a media access priority manager configured to initiate transmission of an indication of a priority of a frame that is to be transmitted onto the shared media.

Physical layer device that connects to a shared media and method for operating a physical layer device that connects to a shared media

Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a central processing unit (CPU) that performs routing related processing on packets prior to sending the packets to one or more destination devices and a switch configured to send packets to the CPU. The switch is configured to, in response to receiving a new packet for the CPU, determine whether a wake-on-frame mechanism is enabled. When the wake-on-frame mechanism is enabled, the switch causes an interrupt signal to be sent to the CPU, such that receiving the interrupt signal will cause the CPU to wake up. When the wake-on-frame mechanism is disabled, the switch sends the packet to the CPU.

Wake-on-frame for frame processing devices

A physical layer circuit includes registers and a timing circuit. The registers are configured to store a future time of day, a local hardware time and a compensation value. The timing circuit is configured to: determine a relationship between the local hardware time and a grandmaster time; select the future time of day; determine a difference between a local clock and a grandmaster clock and set the compensation value equal to the difference; subsequent to determining the difference, enable maintenance of a current time of day; when the local hardware time matches the future time of day, begin updating the current time of day based on the compensation value to match the grandmaster time; and adjust the compensation value to compensate for drift between the current time of day and the grandmaster time.

Maintaining a time of day in a physical layer circuit including compensating for drift away from a grandmaster time

Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves operating an Ethernet media access control (MAC) unit according to a rate specified in an IEEE 802.3 standard and adapting to transmit data to or from the Ethernet MAC unit at an effective data communications rate on a physical media, where the effective data communications rate is different from the rate specified by the IEEE 802.3 standard.

Communications device and method for communications

Embodiments of a device and method are disclosed. In an embodiment, a physical layer (PHY) device that is compatible with the IEEE 802.3 standard is disclosed. The PHY device includes a physical coding sublayer transmitter (PCS-TX), a physical medium attachment transmitter (PMA-TX), a physical coding sublayer receiver (PCS-RX), a physical medium attachment receiver (PMA-RX), and a media access priority manager configured to initiate transmission of an indication of a priority of a frame that is to be transmitted onto a shared media, where the indication of the priority of the frame includes more than three bits of frame priority information.

Physical layer device and method for operating a physical layer device

A switching device is provided and includes a processor and a physical layer device. The processor is configured to generate a synchronization frame and a corresponding follow up frame. The follow up frame is generated while or subsequent to the generating of the synchronization frame and without waiting for an egress timestamp indicating when the synchronization frame is to be transmitted from the switching device to a network device. The physical layer device is configured to: receive the synchronization and follow up frames from the processor; prior to transmitting the follow up frame to the network device, modify the follow up frame to include the egress timestamp indicating when the synchronization frame is transmitted from the switching device via the physical layer device; and perform a precision time protocol process including transmitting the synchronization and follow up frames from the switching device to the network device for clock synchronization.

Bridges including physical layer devices for indicating transmission times of synchronization frames by modifying previously generated corresponding follow up frames

A network device operative to maintain a first time of day (ToD) synchronized to a grandmaster clock is provided and includes a physical layer (PHY) circuit and a processor. The PHY circuit: maintains the first ToD in a first format and a second ToD in a second format; initially sets the second ToD based on a master ToD of the grandmaster clock; and updates the second ToD to maintain synchrony with a master time of the grandmaster clock by incrementing a counter based on a local clock, periodically updating the first ToD responsively to a counter value of the counter, and based on the updated first ToD and a compensation value, periodically adjusting the second ToD to more closely match the master time. The processor ascertains whether the second ToD has drifted from the master time and adjusts the compensation value based on whether the second ToD has drifted.

Maintaining a time of day in physical layer circuit of a network device while periodically compensating for drift away from a master time of a grandmaster clock

Growing community of inventors

Cupertino, CA, United States of America

Donald Robert Pannell