Delco Electronics Corporation

Donald Ray Disney

Wayne Anthony Sozansky

James M Himelick

Stephen P Barlow

John R Fruth

John Robert Shreve

A process for integrating a vertical power device, such as an IGBT device, with suitable control circuitry, such as circuitry that provides self-protection from over-temperature (OT), over-voltage (OV) and over-current (OC) conditions. The process yields a vertical power device that is monolithically integrated with, and dielectrically isolated from, its control circuitry with the use of wafer-bonded silicon-on-insulator (SOI) material that yields a buried oxide layer. The process includes simultaneous fabrication of the power device below the buried oxide layer and its control circuitry above the buried oxide layer, in the SOI layer.

Vertical power device with integrated control circuitry

Method of fabricating a vertical power device with integrated control

A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection. The edge termination structure (110) is formed in the substrate (128) so as to completely surround the interior region (100a) of the substrate (128), and therefore surrounds the power devices (116) to form a continuous barrier structure between the power devices (116) and the over-voltage clamp (118). The edge termination structure (110) includes a main junction (112) and at least one field-limiting ring (114), each of which is formed by a continuous well of the same electrical conductivity type. The edge termination structure (110) also includes a pair of field plates, a first (142) of which contacts the field-limiting ring (114) and a second (138) contacts the polysilicon layer (126) so as to make electrical contact with a gate terminal of the main junction (112).

Edge termination for zener-clamped power device

An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a subsurface P+ region below the entire bottom of an N+ 'source' region of the IGBT. This low resistivity region suppresses thyristor latch-up when contacted via a surface trench. Self-aligned techniques provide method and product improvements.

Method of making a insulated gate bipolar transistor with high-energy P+

Method of making an insulated gate bipolar transistor with high-energy P+ i

An insulated gate electrical load driving device includes simple and accurate gate control circuitry for limiting load current therethrough. Preferably, all circuitry is formed of a single integrated circuit having the insulated gate load driving device dielectrically isolated from the gate control circuitry. The gate control circuitry may include either one, or both, of a zener diode and a resistor divider. An input drive signal to the circuit is accurately controlled by the gate control circuitry to thereby limit the saturation current through the insulated load driving device, and hence the load current, to predetermined current level. Preferably, the predetermined saturation current level falls within a range of saturation currents of the insulated gate load driving device that is substantially constant over a wide operating temperature range.

Electrical load driving device including load current limiting circuitry

A semiconductor device characterized by a field limiting ring formed by a number of field limiting cells that define wells which are laterally diffused to form a continuous equipotential ring between interior and exterior regions of a semiconductor device. A number of active cells are formed in the interior region, and are therefore delineated from the exterior region of the device. Each of these active cells is a transistor, and preferably a field-effect transistor, whose structure is essentially identical to the field limiting cells, except that their wells are not merged but instead are isolated from each other. The field limiting ring increases the breakdown voltage and the ruggedness of device, and therefore enables the device to sustain high voltages when the device is in the off-state. The process does not require masking, implanting and diffusion steps for the sole purpose of forming the field limiting ring, but is instead fully integrated with the semiconductor process for forming the active cells. The field limiting cells also contribute to forward current conduction when the device is in the on-state, thereby lowering the on-resistance of the device.

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Kokomo, IN, United States of America

Donald Ray Disney