Power Integrations, Inc.

Advanced Analogic Technologies Incorporated

Avogy, Inc.

Advanced Analogic Technologies (hong Kong) Limited

Monolithic Power Systems, Inc.

Globalfoundries Singapore Pte. Ltd.

Skyworks Solutions (hong Kong) Limited

Chengdu Monolithic Power Systems Co., Ltd.

Other

Globalfoundries U.S. Inc.

Donald Ray Disney

Richard Kent Williams

Wai Tien Chan

Hui Nie

Isik C Kizilyalli

Richard J Brown

Janardhanan S Ajit

Andrew Paul Edwards

Vladimir Rumennik

Jun-Wei Chen

HyungSik Ryu

Lulu Peng

Sujit Banerjee

Linda T Romano

Lei Zhang

Tiesheng Li

Hemal N Shah

Wayne Bryan Grabowski

Brian Joel Alvarez

Patrick James Lazlo Hyland

David P Bour

Mohamed N Darwish

Thomas R Prunty

Amit Paul

Michael Ren Hsing

Ognjen Milic

Lawrence Selvaraj Susai

Rongyao Ma

Rajesh Sankaranarayanan Nair

Cho Chiu Ma

Jongjib Kim

Wen-Cheng Lin

Alex B Djenguerian

Kiok Boone Elgin Quek

James Copland Moyer

Khee Yong Lim

James Nguyen

Yun Ling Tan

Liang Li

Madhan M Raj

Kai Hung Alex See

Chia Ching Yeo

Kun Yi

Heratch Amirkhani Namagerdi

Valdimir Rumennik

Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate, a plurality of transistors overlying the semiconductor substrate, and an interlayer dielectric layer overlying the plurality of transistors with a metallization layer disposed within the interlayer dielectric layer. The plurality of transistors and the metallization layer form a gate driver circuit. The integrated circuit further includes a plurality of vias disposed through the interlayer dielectric layer, a gate driver electrode coupled to the gate driver circuit, a III-V device electrode overlying and coupled to the gate driver electrode, and a III-V device overlying and coupled to the III-V device electrode.

Integrated III-V device and driver device packages with improved heat removal and methods for fabricating the same

Integrated circuits (ICs) and method for forming IC devices are presented. In one embodiment, a method of forming a device with an integrated magnetic component using 3-dimensional (3-D) printing is disclosed. The method includes providing a substrate with a base dielectric layer, the base dielectric layer serves as a base for the integrated magnetic component. A first metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A magnetic core is formed on the substrate by spray coating magnet powder over the substrate and performing selective laser sintering on the magnet powder. A second metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A patterned dielectric layer separates the first and second metal layers and the magnetic core.

3-dimensional printing process for integrated magnetics

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.

Methods for producing integrated circuits with magnets and a wet etchant for the same

The present disclosure relates to semiconductor structures and, more particularly, to an ultra-high voltage resistor and methods of manufacture. The structure includes at least one resistor coupled to a well of a doped substrate, the at least one resistor being separated vertically from the well by an isolation region with one end of the resistor being attached to an input pad and another end coupled to circuitry.

Ultra-high voltage resistor

The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.

Extended drain MOSFETs (EDMOS)

Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a plurality of transistors in and/or overlying the semiconductor substrate. The plurality of transistors form a gate driver circuit. The integrated circuit further includes a gate driver electrode coupled to the gate driver circuit. Also, the integrated circuit includes a III-V device electrode overlying and coupled to the gate driver electrode. The integrated circuit includes a III-V device overlying and coupled to the III-V device electrode.

Integrated III-V device and driver device units and methods for fabricating the same

Integrated LED and LED driver units and methods for fabricating integrated LED and LED driver units and products with a plurality of integrated LED and LED driver units are provided. In an embodiment, a method for fabricating an integrated LED and LED driver includes forming an LED driver in a first substrate, wherein the first substrate is a semiconductor substrate. The method include forming a bond pad over a top surface of the semiconductor substrate and electrically connected to the LED driver. Also, the method includes forming an LED on a second substrate. Further, the method includes directly coupling the LED to the bond pad.

Integrated LED and LED driver units and methods for fabricating the same

An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.

Saucer-shaped isolation structures for semiconductor devices

Integrated circuits and coupled inductors with isotropic magnetic cores, and methods for fabricating integrated circuits and coupled inductors with isotropic magnetic cores are provided. In an embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate and forming an isotropic magnetic core bottom yoke over the semiconductor substrate. Further, the method includes forming an inductor coil over the isotropic magnetic core bottom yoke. Also, the method includes forming isotropic magnetic core sidewalls over the isotropic magnetic core bottom yoke and around the inductor coil. The method includes forming an isotropic magnetic core top yoke over the isotropic magnetic core sidewalls and over the inductor coil.

Integrated circuits and coupled inductors with isotropic magnetic cores, and methods for fabricating the same

Integrated circuits, methods for fabricating integrated circuits, and methods for fabricating electrical interconnects for III-V devices are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a III-V device over and/or within a semiconductor substrate. The method further includes forming a conductive layer over the semiconductor substrate and electrically connected to the device. The conductive layer has an upper surface. Also, the method includes forming a plurality of dielectric material areas over the upper surface of the conductive layer to define covered portions and uncovered portions of the upper surface of the conductive layer. The method includes depositing an interconnect metal over the plurality of dielectric material areas and over the uncovered portions of the upper surface of the conductive layer. The interconnect metal is electrically connected to the upper surface of the conductive layer.

Integrated circuits and methods for fabricating integrated circuits and electrical interconnects for III-V semiconductor devices

Integrated circuits and coupled inductors with isotropic magnetic cores, and methods for fabricating integrated circuits and coupled inductors with isotropic magnetic cores are provided. In an embodiment, a coupled inductor includes a first inductor coil arranged around a coil center and a second inductor coil arranged around the coil center. The second inductor coil is interleaved with the first inductor coil, and the first and second inductor coils form an interleaved inductor coil. The coupled inductor further includes an isotropic magnetic core surrounding a portion of the interleaved inductor coil and passing through the coil center.

An isolation structure formed in a semiconductor substrate of a first conductivity type includes a floor isolation region of a second conductivity type opposite to the first conductivity type submerged in the substrate. A first trench extends downward from a surface of the substrate and overlaps onto the floor isolation region. The first trench includes walls lined with a dielectric material and contains a conductive material. The first trench and the floor isolation region electrically isolate a pocket of the first conductivity type from the substrate.

Isolation structures for semiconductor devices including trenches containing conductive material

A device and a method for forming a device are disclosed. The device includes a substrate with a high voltage (HV) device region. The HV device region is defined with first and second device isolation regions and an internal dielectric region which are shallow trench isolation (STI) regions. A HV transistor is disposed in the HV device region. The HV transistor includes a gate dielectric layer on the substrate, a gate disposed on the gate dielectric layer, and a source region disposed in the substrate adjacent to the gate and first device isolation region while a drain region disposed in the substrate adjacent to the second device isolation region. A drift well and a body well are disposed in the substrate. At least one buried RESURF region is disposed under the internal dielectric region.

Lateral high voltage transistor

Devices and methods of forming a device are disclosed. The method includes providing a wafer that includes a center insulator layer sandwiched by a top substrate and a bottom substrate. Both sides of the wafer are patterned and etched in sequence to form deep trenches in both substrates. A conductive seed layer is formed on both sides of the wafer in sequence to cover all exposed areas. Both sides of the wafer are electroplated simultaneously to fill both deep trenches with a conductive material. Both sides of the wafer are polished in sequence to form a coplanar surface. A protective layer is deposited on both sides of the wafer in sequence. Selective portions of the protective layer on both sides are patterned and etched in sequence to expose micro bump bonding areas. Micro bumps are formed on both sides of the wafer in sequence to facilitate electrical connection.

High voltage device

Growing community of inventors

Cupertino, CA, United States of America

Donald Ray Disney