Hewlett-packard Company

Other

Hewlett-packard Development Company, L.p.

Globalfoundries Inc.

Advanced Micro Devices Corporation

Donald R Weiss

John J Wuu

Samuel D Naffziger

Reid James Riedlinger

Damon Germanton

Richard Thomas Schultz

Kevin X Zhang

Russell J Schreiber

Jay E Fleischman

William McGee

J Michael Hill

Richard L Woodruff

John Reginald Riley

Blaine Stackhouse

Jeffery C Brauch

Charles E Germanton

Charles Morrganti

Shyang-Tai Su

Michael A Dreesen

A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M&#x2212;A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Sidecar SRAM for high granularity in floor plan aspect ratio

A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Method and apparatus for providing complimentary state retention

In operation the storage device of this invention is an attachment to a player/recorder such as an iPhone or iPod. The storage device allows the user to record content, store it on the storage device, retrieve the content, and display/play the content on the host device. The software may come pre-loaded on the storage device. The storage chip may have an adhesive back and comes in different colors, shapes and sizes.

Memory chip device

A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.

Error detection device and methods thereof

Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

SRAM bit cell with self-aligned bidirectional local interconnects

A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide a current to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.

Sensing device for floating body cell memory and method thereof

According to one embodiment, a method comprises detecting a defect in a portion of memory. The method further comprises designating the portion of memory as defective, and avoiding attempts to access the portion of memory designated as defective.

System and method for avoiding attempts to access a defective portion of memory

The present invention employs a bias voltage having a selectable magnitude to bias a weak write pull-down transistor in a write driver of a static random access memory (SRAM) array. A programmable weak write test mode (PWWTM) bias generator includes an output signal that is a logic high in a default mode when a WWTM is not active. When the WWTM is active, the generator output signal is the bias voltage having the selectable magnitude. The default mode logic high is actively maintained when the generator output is connected to a load, such as the write driver of the SRAM array. A WWTM-enabled SRAM system includes the PWWTM bias generator. A method of driving a WWTM-equipped SRAM includes generating and applying the output signal to a gate of a weak write pull-down transistor of the SRAM array write driver in the default mode and the WWTM.

Programmable weak write test mode (PWWTM) bias generation having logic high output default mode

According to at least one embodiment, a method comprises measuring drive current of a reference memory cell of a circuit, and determining, based on the measured drive current of the reference memory cell, a drive current to be supplied to a calibration memory cell of the circuit to mimic a defective memory cell. The method further comprises supplying the determined drive current to the calibration memory cell, and using the calibration memory cell to determine strength of a weak write to be utilized by a weak write test for detecting defective memory cells.

System and method for calibrating weak write test mode (WWTM)

A system and method are disclosed which provide a built-in self test (BIST) for a content addressable memory (CAM) structure. In a preferred embodiment, an integrated circuit (chip) comprises a CAM structure that is accessible by a processor to satisfy memory access requests and a BIST implemented within such chip, which enables testing the integrity of the CAM structure. Such a preferred embodiment comprises a BIST that enables testing the integrity of the CAM structure that does not require circuitry for reading memory data out of the CAM structure. A preferred embodiment can also be utilized for testing a random access memory structure. In a preferred embodiment, a CAM BIST comprises logic capable of generating test values (e.g., a test pattern), a shift register that temporarily stores the test values generated by the logic, and compare circuitry that determines whether a test value matches an entry within the CAM structure.

Built-in self test for content addressable memory

A system and method which implement a memory component of an integrated circuit as multiple, relatively small sub-arrays of memory to enable great flexibility in organizing memory within the integrated circuit are provided. In a preferred embodiment, the memory component of an integrated circuit is implemented as multiple, relatively small sub-arrays of memory, which enable a designer great flexibility in arranging such sub-arrays within an integrated circuit. Also, in a preferred embodiment, the memory component of an integrated circuit is implemented as multiple memory sub-arrays that are each independent. For example, in a preferred embodiment, each memory sub-array comprises its own decode circuitry for decoding memory addresses that are being requested to be accessed by an instruction, and each memory sub-array comprises its own I/O circuitry. In one implementation of a preferred embodiment, each of the independent memory sub-arrays implemented in an integrated circuit comprises no more than approximately five percent of the total memory implemented on the integrated circuit. In another implementation, each of the independent memory sub-arrays on an integrated circuit is no larger than approximately the average size of other non-memory components implemented on the integrated circuit. Additionally, in further implementation, the memory component of an integrated circuit comprises at least a 20 independent memory sub-arrays. Therefore, in a preferred embodiment, each independent sub-array is relatively small in size to enable great flexibility in organizing the memory on an integrated circuit. Furthermore, because each sub-array is independent, greater flexibility is available in repairing defects through redundancy.

Flexible cache architecture using modular arrays

A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder accepts an addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder also outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include logic to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any single memory cell in the SRAM cell for reading or writing specific logical states.

Static random access memory (SRAM) array central global decoder system and method

A single-ended read, differential write CMOS SRAM cell has two inverters connected in a regenerative feedback circuit. Each inverter includes two complementary FETs. FETs of the same type in each inverter have differing gate widths and/or drive currents. The cell includes pass gate FETs having gate regions of approximately the same widths but differing lengths.

Asymmetric RAM cell

A circuit for signalling if any like ordered bits A,and B,in first and second binary words differ comprises a comparator for each pair of like ordered bits and a common terminal. Each comparator includes first and second FETs arranged so: (a) the first and second levels of A,are coupled to the common terminal via the first FET in response to B,having the first value, (b) the first and second levels of B,are coupled to the common terminal via the second FET in response to A,having the first value, (c) the first FET decouples A,from the common terminal and tends to cause the common terminal to be at the second level in response to B,having the second value, (d) the second FET decouples B,from the common terminal and tends to cause the common terminal to be at the second level in response to A,having the second value, and (e) the common terminal is at the second level only in response to A,[object Object]

Multi-bit comparator

A system and method are provided which enable a data carrier, such as a BIT line, to be held to a desired value while performing a memory access (e.g., a read or write operation) of SRAM in an efficient manner. In a preferred embodiment, cross-coupled PFETs are implemented to hold the BIT line to a desired value during a memory access of SRAM. As a result, a preferred embodiment enables a BIT line to transition from a high voltage value to a low voltage value free from conflict. That is, in a preferred embodiment, a holder PFET is not attempting to hold the BIT line high, while the SRAM or outside source (e.g., a &ldquo;writing source&rdquo;) is attempting to drive the BIT line to a low voltage value. Also, in a preferred embodiment, the BIT and NBIT lines (i.e., a complementary data carrier) can be driven to &ldquo;true&rdquo; low and &ldquo;true&rdquo; high voltage values. Accordingly, in a preferred embodiment, complex circuitry, such as a sense amp, is not required to detect whether a value on the lines is a logic 0 or logic 1. Therefore, a preferred embodiment enables memory access requests (e.g., read and write operations) to be serviced in a more timely manner than is achieved utilizing prior art implementations. Furthermore, a preferred embodiment requires less power consumption than is required for prior art implementations. Moreover, a preferred embodiment utilizes fewer components, and therefore consumes less surface area than in prior art implementations.

Growing community of inventors

Fort Collins, CO, United States of America

Donald R Weiss