Honeywell Information Systems Inc.

Donald R Taylor

Arthur A Parmet

Philip E Stanley

David E Cushing

John L Curley

C William Dawson

A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store. In addition, the elements included in the upper bank are selected to have address propagation time sufficiently faster than the address propagation time of the lower bank to compensate for the additional logic propagation delay introduced by the multiplexer so that the contents of the addressed locations of the upper and lower banks are available for use by the system at substantially the same time.

Control store organization for a data processing system

A system and method for providing a control store arrangement in which a single memory having a plurality of memory locations can be used for storing sequences of microinstructions or scratch pad information. The number of storage locations defining the scratch pad area can be increased or decreased as required by assigning tag addresses to a desired number of scratch pad storage locations when the microinstruction routines are being assembled. In this manner, the locations defining the scratch pad areas can be tailored to the particular system operation to be performed. This eliminates the need for modifying the control store circuits to change the size of the control store scratch pad area.

Control store system and method for storing selectively

A host system includes a microprogrammed processing unit which couples a foreign processing unit to the main memory of the host system. The microprogrammed processing unit also couples to an interface connected to the foreign processor. During operation, the host processor transfers a channel command to the microprogrammed processing unit which is operative under firmware control to perform the various control functions required for initiating a particular job. In this manner, the various parameters and information necessary to dispatch a job of the foreign processor is accomplished expeditiously under the firmware control in response to commands issued by the host processor.

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Framingham, MA, United States of America

Donald R Taylor