Candescent Technologies Corporation

Synaptics Corporation

Other

Candescent Intellectual Property Services, Inc.

Advanced Technology Materials, Inc.

Canon Kabushiki Kaisha

Donald R Schropp, Jr

James C Dunphy

Michael James Nystrom

Roger W Barton

Shiyou Pei

George B Hopple

Kollengode S Narayanan

Lawrence S Pan

Christopher J Spindt

Bob Lee Mackey

Xueping Xu

John M Macaulay

Sudhakar Gopalakrishnan

Ramamoorthy Ramesh

John E Field

David L Morris

David R Morris

Ronald S Besser

John K O'Reilly

Vasil M Chakarov

Automotive acceleration compensation force sensing includes determining a total force value from the measurements from force sensors, obtaining, from an accelerometer, an environmental acceleration value, and calculating an input object force value on an input surface using a total force value and the environmental acceleration value. Automotive acceleration compensation force sensing further includes reporting the input object force value.

Automotive acceleration compensation force sensing

Sensing systems and methods that utilize lower-order zero row sum code division multiplexing (CDM) drive matrices to reduce or eliminate radiative emissions. Measurements corresponding to an input received at a sensing region of the input device are obtained by separately driving multiple subsets of transmitters of the input device, and obtaining measurement values corresponding to each separately-driven subset of transmitters via the receivers, wherein a plurality of measurement iterations are performed for each separately-driven subset of transmitters, the plurality of measurement iterations corresponding to a zero row sum CDM drive matrix for the separately-driven subsets of transmitters. An image of the input is generated based on the obtained measurements.

Input sensing using code division multiplexing (CDM)

A method may include obtaining a capacitive image of various sensor pixels in an input device. The capacitive image may include various capacitive measurements resulting from the first input object and the second input object in a sensing region of the input device. The method may further include obtaining various pixel response functions corresponding to the sensor pixels. The method may further include determining, from the capacitive image and using a search method and the pixel response functions, various capacitive contributions of the first input object in the capacitive image and various capacitive contributions of the second input object. The method may further include determining, using the capacitive contributions of the first input object and the capacitive contributions of the second input object, a first location of the first input object and a second location of the second input object.

Method and system for input object separation using pixel response functions

In a method of input sensing and exclusion, an input is detected within a sensing region of an input device. It is determined that the input is along an edge of the input device. It is then determined whether the input satisfies exclusion criteria. Responsive to satisfaction of the exclusion criteria, the input is excluded from consideration as valid input.

Input sensing and exclusion

A flat-panel display is fabricated by a process in which a spacer () having a rough face (or) is positioned between a pair of plate structure (and). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as providing suitable depressions (, or) or/and protuberances (, and) along the spacer's face.

Fabrication of flat-panel display having spacer with rough face for inhibiting secondary electron escape

The present invention provides a spacer assembly which is tailored to provide a secondary electron emission coefficient of approximately 1 for the spacer assembly when the spacer assembly is subjected to flat panel display operating voltages. The present invention further provides a spacer assembly which accomplishes the above achievement and which does not degrade severely when subjected to electron bombardment. The present invention further provides a spacer assembly which accomplishes both of the above-listed achievements and which does not significantly contribute to contamination of the vacuum environment of the flat panel display or be susceptible to contamination that may evolve within the tube. Specifically, in one embodiment, the present invention is comprised of a spacer structure which has a specific secondary electron emission coefficient function associated therewith. The material comprising the spacer structure is tailored to provide a secondary electron emission coefficient of approximately 1 for the spacer assembly when the spacer assembly is subjected to flat panel display operating voltages.

Tailored spacer wall coatings for reduced secondary electron emission

A flat-panel display contains a pair of plate structure ( and ) separated by a spacer ( ) having a rough face ( or ). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as depressions ( , or ) or/and protuberances ( , and ). Various techniques are presented for manufacturing the display, including the rough-faced spacer.

Flat-panel display having spacer with rough face for inhibiting secondary electron escape

The intensity at which electrons emitted by a first plate structure ( ) in a flat-panel display strike a second plate structure ( ) for causing it to emit light is controlled so as to reduce image degradation that could otherwise arise from undesired electron-trajectory changes caused by effects such as the presence of a spacer system ( ) between the plate structures. An electron-emissive region ( ) in the first plate structure typically contains multiple laterally separated electron-emissive portions ( and ) for selectively emitting electrons. An electron-focusing system in the first plate structure has corresponding focus openings ( P and P ) through which electrons emitted by the electron-emissive portions respectively pass. Upon being struck by the so-emitted electrons, a light-emissive region ( ) in the second plate structure emits light to produce at least part of a dot of the display's image.

Flat-panel display with intensity control to reduce light-centroid shifting

In a field emission display device, a spacer assembly and a method for forming a spacer assembly. In one embodiment, the present invention is comprised of a spacer wall which has a specific secondary electron emission coefficient function associated therewith. In the present embodiment, a coating material is then applied to at least a portion of the spacer wall. In this embodiment, the coating material has a secondary electron emission coefficient function which is different than the secondary electron emission coefficient function of the spacer wall. In so doing, the present embodiment provides a spacer assembly having a plurality of secondary electron emission coefficient functions associated therewith.

Tailored spacer structure coating

A voltage ratio regulator circuit for a spacer electrode of a flat panel display screen. Within one implementation of a field emission display (FED) device, thin spacer walls are inserted between a high voltage (Vh) faceplate and a backplate to secure these structures as a vacuum is formed between. A phosphor layer on the faceplate receives electrons selectively emitted from discrete electron emitting areas along the backplate (cathode) thereby forming images on the faceplate. The faceplate warms relative to the backplate, as a result of energy released by the phosphor layer, thereby generating a temperature gradient along the spacer walls. The top portion of each spacer wall becomes more conductive with increased temperature and acts to attract electrons that are emitted toward the faceplate. To counter this attraction, a spacer electrode is placed along each spacer wall at a height, d, above the backplate and maintained at a voltage, Ve. Electrodes of all of the spacer walls are coupled together. The spacer electrode at Ve and the high voltage supply at Vh are both coupled to a voltage ratio regulator circuit which maintains the ratio (Ve/Vh) using voltage dividers, an operational amplifier and other circuitry. The voltage ratio regulator compensates for variations in voltage supply performance. The time constants of the voltage ratio regular circuit is tuned to be near or slightly faster than the time constant of the inherent resistance and capacitance of the spacer wall. The invention can also correct for other sources of the voltage error on the spacer walls. The invention improves the electron path accuracy for pixels located near spacer walls.

Growing community of inventors

San Jose, CA, United States of America

Donald R Schropp, Jr