Rambus Inc.

Donald R Mullen

Ming Chu Li

Frederick Abbott Ware

Belgacem Haba

Kevin S Donnelly

Gary Bela Bronner

David A Secker

Sayeh Khalili

Thomas J Giovannini

Donald Victor Perino

Abhijit Mukun Abhyankar

Haw-Jyh Liaw

Ravindranath T Kollipara

Chi-Ming Yeung

Arun Vaidyanath

Nader Gamini

Adrian F Torres

A rack unit configuration is described that includes a first printed circuit board (PCB) assembly interleaved with a second PCB assembly that is inverted with respect to the first PCB assembly. The configuration of the first PCB assembly and the second PCB assembly allow for increased component and power densities within computing systems, memory systems, etc. The increased density may be achieved while allowing sufficient mechanical clearance to allow easy component replacement and servicing (e.g., and hot pluggability). Power density may also be increased with PCB assemblies including nested and interleaved power modules.

Circuit board assembly configuration

A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.

Memory capacity expansion using a memory riser

A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.

Repairing defects in a nonvolatile semiconductor memory module utilizing a heating element

A system includes a circuit board, a multi-die package, and a heat dissipator. The circuit board has substantially planar opposing first and second sides. The multi-die package includes a substrate and a first set of one or more semiconductor devices on a first substrate side and a second set of one or more semiconductor devices on a second substrate side. The multi-die package is located at the first circuit board side. The heat dissipator is located at the second circuit board side, and thermally coupled to the second set of semiconductor devices. One or more portions of the circuit board are removed between the first circuit board side and the second circuit board side so as to define one or more holes through the circuit board and to facilitate thermal coupling between the second set of semiconductor devices and the heat dissipator through the one or more holes.

System and method for dissipating heat from semiconductor devices

A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.

Repairing defects in a nonvolatile semiconductor memory device utilizing a heating element

The system includes a circuit board, a semiconductor module, a heat dissipator, and at least one thermal via. The circuit board has substantially flat opposing first and second sides. The semiconductor module includes multiple semiconductor devices. The semiconductor module is oriented substantially parallel to the circuit board near the first side, while the heat dissipator is disposed near the second side. The thermal via extends through the circuit board to thermally couple the semiconductor module to the heat dissipator, which may be a heat spreader, heat sink, cooling fan, or heat pipe.

System and method for dissipating heat from a semiconductor module

The semiconductor package includes two electrical contacts and a semiconductor device coupled to opposing sides of a substrate. The substrate defines at least one via extending at least partially there through. The semiconductor device includes a semiconductor low-speed interface electrically coupled to one of the electrical contacts through the via, and a semiconductor high-speed interface electrically coupled to flexible tape. The flexible tape is also electrically coupled to the other one of the electrical contacts.

Semiconductor package with low and high-speed signal paths

An integrated circuit cover incorporating a spring portion is described. The spring portion may include any structure that allows displacement between a plate portion of the integrated circuit cover and an attachment portion of the integrated circuit cover and that provides a substantially equalizing effect of pressure on the plate portion. The spring portion is preferably more flexible than the plate portion. The integrated circuit cover accommodates variations in the mounted height of integrated circuits over which the integrated circuit cover is installed The integrated circuit cover may be formed as a unitary structure or may be constructed as an assembly of multiple components.

Method and apparatus for providing an integrated circuit cover

A memory architecture includes a first substrate containing multiple memory devices and a first channel portion extending across the first substrate. The architecture further includes a second substrate containing multiple memory devices and a second channel portion extending across the second substrate. A connector couples the first channel portion to the second channel portion to form a single channel. The connector includes a first slot that receives an edge of the first substrate and a second slot that receives an edge of the second substrate. Another connector has a pair of slots that receive opposite edges of the first and second substrates. The channel portions extend across the substrates in a substantially linear path. Each channel portion includes multiple conductors having lengths that are approximately equal.

Multi-channel memory architecture

An electronic device includes a standard dielectric material and a lossy material integrated with the standard dielectric material to selectively control the distributed resistance of the standard dielectric material. The lossy material may be inserted into the standard dielectric material. The inserted material may be resistive particles, carbon particles, open cell conductive foam, carbon impregnated open cell conductive foam, and the like. The lossy material may also be a loss inducing physical structure attached to the standard dielectric material. The loss inducing physical structure may be a planar resistive layer attached to the standard dielectric material. The planar resistive layer may have an extended surface to attenuate high frequency signals.

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Mountain View, CA, United States of America

Donald R Mullen