Broadcom Corporation

Compaq Computer Corporation, Inc.

Donald P Matthews

Mark Leonard Buer

Joseph John Tardo

Ralph Bestock

Methods and apparatus are provided for decoupling a cryptography accelerator interface from cryptographic processing cores. A shared resource is provided at the cryptography accelerator interface having multiple input ports. References to data in the shared resource are provided to allow processing and ordering of data in preparation for processing by cryptographic processing cores without substantial numbers of separate buffers in the cryptographic processing data paths.

Cryptography accelerator interface decoupling from cryptography processing cores

Methods and apparatus are provided for handling data at a cryptography accelerator output interface. A shared resource such as a shared output buffer is provided at the cryptography accelerator output interface having multiple output ports. The output interface shared resource can be allocated amongst the various output ports based on characteristics and requirements of the various input ports. References to data in the shared resource allow processing and ordering of data following processing by cryptographic processing cores.

Cryptography accelerator data routing unit

Methods and apparatus are provided for improving ARC4 processing in a cryptography engine. A multiple ported memory can be used to allow pipelined read and write access to values in memory. Coherency checking can be applied to provide that read-after-write and write-after-write consistency is maintained. Initialization of the memory can be improved with a reset feature occurring in a single cycle. Key shuffle and key stream generation can also be performed using a single core.

Methods and apparatus for accelerating ARC4 processing

Methods and apparatus are provided for a cryptography accelerator to efficiently perform authentication and encryption operations. A data sequence is received at a cryptography accelerator. An encrypted authentication code and an encrypted data sequence is provided efficiently upon performing single pass authentication and encryption operations on the data sequence.

Methods and apparatus for performing encryption and authentication

Method and apparatus is provided for securely configuring a programmable hardware device from a remote source. The programmable hardware device includes a plurality of programmable logic modules. A host receives configuration information from the remote source, where the configuration information defines a function of the programmable logic modules. The host encrypts the configuration information according to a cryptographic algorithm. The encrypted information is transferred to a special download engine at the programmable hardware device, which decrypts the information according to the same cryptographic algorithm. The programmable logic modules are thus configured by the decrypted configuration information, which has been securely downloaded from the remote source.

Encrypted download of SRAM-based FPGAs

A keyboard input device includes a processor repeatedly executing a scan routine to detect key press events while masking the events from an external monitoring means. The keyboard input device has a number of finger-activatable keys, each connected at the intersection of row signal lines and column signal lines, which are in turn connected to the processor. The processor systematically activates the rows and randomly activates the columns. A key press event causes the key's associated row and column to create a closed switch. The processor monitors the columns for a signal forced on pairs of rows. Obfuscating signals forced onto the columns inhibit detection of the key press event signals by an external source.

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Morgan Hill, CA, United States of America

Donald P Matthews