International Business Machines Corporation

Donald Norman Senzig

Martin Stanley Schmookler

Gordon J Robbins

The present invention discloses a microprocessor bus structure that enables a processor chip to be designed with optional unidirectional or bi-directional I/O buses. The processor is designed with separate input and output bus internal to the chip. A gating network is coupled to these processor uni-directional busses that allows the chip to have an alternate externally wired bus structure. For the lowest cost and lowest performance only one set of bidirectional bus lines are wired external to the chip. These lines have a parallel driver and receiver with appropriate gating to allow the bus to be either in the send or receive mode. The signals from the processor uni-directional input and output buses are wired via appropriate gating to create a single bi-directional bus. For high performance operation where higher cost for higher bandwidth is justified, the bidirectional bus is gated to be a device output only bus and the alternate device input bus is gated to the processor input bus creating a true uni-directional bus structure. The bus enable line is wired to the appropriated stated depending on the wired microprocessor bus structure.

Microprocessor bus structure

An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1&lE;&times;<2, and one lookup table is used, having an interval size of {fraction (1/32)}. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table). In another implementation, the input value is normalized within the range 0.5&lE;&times;<2, and two lookup tables are used, a first table having an interval size of {fraction (1/32)} for the range 0.5&lE;&times;<1, and a second table having an interval size of {fraction (1/16)} for the range 1&lE;&times;<2.

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Austin, TX, United States of America

Donald Norman Senzig