Adaptec, Inc.

Donald N Allingham

Patrick R Bashford

Eric S Noya

Michael Joseph Peters

Ralph F Ware, Jr

Paul S Grist

The present invention provides bridge device for transferring data using master-specific prefetch sizes. The bridge device is coupled between a first bus and a second bus with the master devices being coupled to the first bus and the slave devices being coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the master devices with one prefetch control register being provided for a master device. The prefetch buffer is arranged to store data for transfer. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring data between a source device and a destination device. The bridge control circuitry is further arranged to receive a first data transfer request from a selected master device for transferring data between the selected master device and a selected slave device. The bridge control circuitry issues a second data transfer request to the selected slave device for transferring the data. The bridge control circuitry receives the requested data from the source device and stores the received data in the prefetch buffer. The bridge control circuitry transfers the stored data from the prefetch buffer to the destination device when the prefetch buffer receives and stores data size that correspond to the prefetch size stored in a prefetch control register associated with the selected master device.

Bridge device for transferring data using master-specific prefetch sizes

The present invention provides a RAID controller coupled to a host computer system through a primary PCI bus. The RAID controller includes a PCI application bridge, a RAID processor and chipset, and an expansion ROM. The PCI application bridge is coupled to interface data and command transfers between the primary PCI bus and a secondary PCI bus. The RAID processor and chipset is coupled to said secondary PCI bus for controlling access to said one or more RAID arrays. The expansion ROM is configured to store device specific codes and BIOS codes for initializing said RAID controller and said host computer system for boot-up. For initializing said RAID controller, the said RAID processor and chipset accesses said device specific codes in said expansion ROM. The RAID processor and chipset provides a first address corresponding to said BIOS codes in said expansion ROM to said PCI bus application bridge. The PCI application bridge translates a host address from said host computer system using said first address to access said BIOS codes for initializing said host computer system.

Intelligent expansion ROM sharing bus subsystem

A scalable memory controller for use in connection with error correction code is provided. According to the invention, the channels of the controller are interconnected to a plurality of parity engines and associated cache memories using a switched fabric architecture. A processor is provided for allocating operations requiring access to the parity engines or cache memories. By providing multiple parity engines and cache memories, error correction syndrome values can be calculated in parallel. The performance of the controller can be selectively scaled by providing a greater or lessor number of parity engines and associated cache memories. Furthermore, by utilizing a switched fabric internal architecture, data transfers between the internal components of the controller can be conducted simultaneously.

Method and apparatus for scalable error correction code generation performance

The invention provides for clearing a delayed transaction buffer associated with master-to-slave transactions on a PCI bus. In a slave such as a PCI bridge chip, or in other slave VLSI devices on the PCI bus, one or more delayed transaction buffers are used to store delayed transaction data to improve bus performance when the master retries a past transaction. A counter section counts time via clock cycles following receipt of a delayed transaction within each buffer. After a preselected time period, the buffer is flushed so that other delayed transaction data can be stored within the buffer. In the preferred embodiment, a free running n-bit counter and a plurality m-bit time out counters are used to provide the &ldquo;time out&rdquo; feature of the invention. Each time out counter generates a flush signal which deletes delayed transaction information stored within the associated buffer after the preselected time out period. The time out counters are reset to &ldquo;zero&rdquo; after receipt of a delayed transaction by the associated delayed transaction buffer.

PCI delayed transaction time out counter and associated methods

The high-speed, multi-device PCI bus communication system of the invention includes a host CPU and a chip set for connecting the host CPU to a first, low speed PCI bus. The chip set has an accelerated graphics port. A VLSI device such as a RAID cache controller includes two PCI interfaces for communicating with second and third, higher speed PCI buses, and includes an accelerated graphics interface for communicating with the accelerated graphics port. A first PCI bridge provides for communication between the accelerated graphics interface and the first PCI interface; and a second PCI bridge provides for communication between the accelerated graphics interface and the second PCI interface. A dedicated communication bus connects the accelerated graphics interface to the accelerated graphics port. A RAM port can connect the VLSI device to external RAM. The system provides for coupling multiple (e.g., six) high speed SCSI devices to the second and third buses, operating at 66 MHz or more, and for coupling utility devices (e.g., ISA devices) to the first PCI bus operating at lesser speeds, e.g., 33 MHz. Communication between the host CPU and the RAID controller is performed over the dedicated communication bus directly through the chip set AGP, thereby freeing up the first, low-speed PCI bus for use with lower-speed utility devices and not impacting other RAID data traffic.

High speed RAID cache controller using accelerated graphics port

The invention provides a PCI bridge chip for communicating command data between a primary PCI bus and a secondary PCI bus. A primary command transaction logic manages command data transfers from the primary PCI bus to the secondary PCI bus. The primary delayed transaction logic has a plurality of primary buffers for buffering command transactions to be issued on the secondary PCI bus selectively. A secondary command transaction logic manages command data transfers from the secondary PCI bus to the primary PCI bus. The second delayed transaction logic has a plurality of secondary buffers for buffering command transactions to be issued on the primary PCI bus selectively. The primary and secondary command transaction logic can for example include three buffers to buffer transaction commands in the appropriate direction. The bridge chip further provides for coupling large burst data through a memory section and to external an external RAM (or alternatively internal memory).

PCI bridge for optimized command delivery

A design verification system for simulating designs and evaluating the simulation results against a set of expected events. A set of expected events are generated and loaded into an expect buffer. As the simulation proceeds, each modelled device collects data on each event into an event record. Each event record is compared against the set of expected events. If the set of expected events contains an entry that matches the event record, the matching entry is removed from the expect buffer. If a matching entry is not found then the event record is flagged as an error. The system is flexible to design changes and efficient as the exact ordering of events is not critical to the simulation outcome.

Design verification system using expect buffers

A bus to bus bridge deadlock prevention system detects and resolves a deadlock condition in a bus to bus bridge. In a PCI protocol application of the present invention, the system detects a retry of a request by a master device. The request is masked for a delay period before the request is allowed to attempt to pass through a PCI to PCI bridge. If the request results in a further retry, the delay period length is changed and the request is masked for the different delay period. Successive retry requests are masked for different delay periods until the deadlock condition is resolved. The system adapts to the deadlock condition by repeatedly changing the delay period until the deadlock condition is resolved and the bridged busses resume normal operation.

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Fort Collins, CO, United States of America

Donald N Allingham